Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Mosaid Technologies Corporation

Matsushita Electronics Corporation

Hirohito Kikukawa

Hironori Akamatsu

Masashi Agata

Shunichi Iwanari

Akihiro Sawada

Hisakazu Kotani

Toshio Yamada

Masanori Shirahama

Yasuhiro Agata

Yasue Yamamoto

Toshiaki Kawasaki

Ichiro Nakao

Ryuji Nishihara

Shinichi Sumi

Kiyoto Ohta

Tomonori Fujimoto

Hiroyuki Yamauchi

Kazuhiro Matsuyama

Cynthia Mar

Fangxing Wei

A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.

System LSI

In a semiconductor memory device including resistance change memory devices, when a resistance change memory device is in standby mode, the two terminals of the resistance change memory device, i.e., a bit line and a source line, are set at a precharge potential Vp, respectively. At the time of a set operation, the bit line is set to a set voltage Vd, which is higher than the precharge potential Vp, while the source line is grounded. At the time of a reset operation, bit line is grounded, while the source line is set to the set voltage Vd. At the time of a data-read operation, the source line is grounded by a read bias generation circuit, while the potential of the bit line is kept at the precharge potential Vp.

Semiconductor memory device and semiconductor integrated circuit system

Electrical fuse blocks () of a plurality of stages are provided each of which includes a plurality of electrical fuse cores (). The electrical fuse block () includes a program shift register block () made up of shift registers () which are disposed for the respective electrical fuse cores (), sequentially transmit program enable signal FPGI, and output the program enable signal FPGI to the NMOS transistors () of the electrical fuse cores (). When performing programming according to programming decision signal PBn, the program shift register block () transmits the program enable signal FPGI. When not performing programming, the program shift register block () skips the program enable signal FPGI.

Semiconductor storage device including electrical fuse module

In a semiconductor device that needs a refresh operation for storing data, data of memory cells selected in response to a row address is read to main amplifiers through bit line pairs, sense amplifiers and data line pairs in a page-mode read operation. Thereafter, while outputting the data held in the main amplifiers to the outside, connecting transistors are turned off so as to disconnect the main amplifiers from the memory cells, and thus, the memory cells can be precharged. Also, in a page-mode write operation, while writing externally supplied input data in the main amplifiers, the memory cells can be precharged.

Semiconductor device having read and write operations corresponding to read and write row control signals

A row control circuit of a semiconductor memory device includes an oscillator as a clock oscillator for generating an internal clock, a D flipflop as a refresh request signal RFRQ generation circuit for generating a refresh request signal RFRQ synchronously with the internal clock, and a delay circuit, a NAND gate, an AND gate, a D flipflop, a delay circuit, an AND gate and an OR gate as refresh circuits. By using a refresh request signal RFRQ and an active signal ACT, internal refresh is performed internally in a DRAM separately from an external refresh command.

Semiconductor memory device and semiconductor integrated circuit device

The invention discloses a synchronous DRAM having memory elements arranged in rows and columns, the memory elements being accessible by decoding a memory address applied thereto, normal column drivers for activating appropriate memory elements in response to decoded column addresses signals; redundant column drivers distributed throughout memory banks and flexibly selectable to replace faulty columns within multiple blocks within a bank; and switch means for selectively activating the redundant column and preventing the activation of a defective normal column, whereby the column redundancy method and apparatus minimizes the timing difference between a normal and redundant column paths and which minimizes the number of fuses required to be blown in repairing faulty columns addresses.

Column redundancy circuit with reduced signal path delay

To restrain an increase in power consumption and a reduction in access speed, the following structure is adopted: An address is input to a row address input circuit and in correspondence with a row address output from the row address input circuit, a predecode signal is output from a row predecode circuit. An address is input to a block-select-signal generating circuit from which first and second block select signals are output for selecting either one of the first and second memory cell array blocks. First and second predecode-signal hold circuits provided in correspondence with the first and second memory cell array blocks hold predecode signals. First and second predecode signals held by the first and second predecode signal hold circuits are supplied to first and second row decode circuits, respectively, and the first and second predecode-signal hold circuits corresponding to the first and second block select signals update the contents being held.

Semiconductor memory device

In a synchronous DRAM, a redundancy judging circuit has a frequency dividing circuit and a plurality of judging circuits each having two address comparing circuits and one output circuit. When an internal CAS signal having an activating period of time according to a data burst length, is activated, the frequency dividing circuit divides the frequency of an internal continuous clock signal having the same time period of one cycle and the same phase as those of an external clock signal, and generates complementary clock signals each having a time period of one cycle twice the time period of one cycle of the internal continuous clock signal. A pair of address comparing circuits to which supplied is an internal column address to be successively updated according to the data burst length, alternately supply a redundancy judgement signal after alternately comparing the same defective column address previously programmed therein, with an internal column address according to the complementary clock signals supplied from the frequency dividing circuit. The output circuit supplies a redundancy judgement signal when either of the judgement signals is obtained. Thus, there is made an accurate column redundancy judgement at the time when the external clock signal is high in frequency.

Semiconductor memory

In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Data transmission circuit, data line driving circuit, amplifying

Semiconductor integrated circuit with a data transmission circuit

In a synchronous DRAM required to be capable of performing high-speed consecutive operations in synchronism with a clock signal, a DBI-line pair is connected between a DQ-line pair and an RDB-line pair, and pipeline operation whose single cycle time is divided into four periods is employed. This S-DRAM has following: a first precharge circuit for precharging or voltage-equalizing the DQ-line pair to a power supply voltage level in the first and forth periods only; a second precharge circuit for voltage-equalizing the DBI-line pair to a ground voltage level in the first and second periods only; a third precharge circuit for voltage-equalizing the RDB-line pair to the power supply voltage level in the first and second periods only; first and second differential amplifiers for transmitting data on the DQ lines onto the DBI lines in the third period and for holding the data on the DBI lines in the fourth period; and a third differential amplifier which transmits the data on the DBI lines onto the RDB lines in the third period and which holds the data on the RDB lines in the fourth period.

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Osaka, Japan

Hirohito Kikukawa