Fujitsu Corporation

Kosugi, Toru

Miyaou, Hirohisa

Furukawa, Takahiro

Hirohisa Miyaou

Toru Kosugi

Takahiro Furukawa

A B8ZS.B6ZS coding circuit commonly used for a B8ZS coding or a B6ZS coding, generating a B8ZS violation signal or a B6ZS violation signal at a same start timing, and formed by a smaller circuit. The B8ZS.B6ZS coding circuit includes a first eight-bit shift register, receiving the input unipolar signal and shifting the same in response to a clock signal, the last two flip-flops in the shift register being reset under the B6ZS mode, a first gate outputting a first consecutive zero detection signal when all flip-flops in the first shift register are reset, a second seven-bit shift register, the last two flip-flops in the shift register being reset under the B6ZS mode, a second gate outputting a second consecutive zero detection signal when all flip-flops in the second shift register are reset, a third gate outputting an exclusive OR signal of the first and the second consecutive zeros detection signals, an inverter and outputting an inverted signal of the output from the third gate, a fourth gate receiving outputs from a sixth flip-flop in the first shift register, first, second, fourth and fifth flip-flops in the second shift register, and outputting a first original coded signal, and a fifth gate receiving outputs from the sixth flip-flop in the first shift register, the inverter, and the first, fourth and fifth flip-flops in the second shift register, and outputting a second original coded signal.

Bipolar with eight-zeros substitution and bipolar with six-zeros

A digital data multiple conversion system which can be used in a digital data communication network and recover lost clock pulses. The system includes a memory unit storing input data having N bits, a first frequency divider frequency-dividing an input clock having a first frequency at N to output a first frequency-divided signal, a first pulse width expansion circuit connected to receive m frequency divided pulses from the first frequency divider, where m indicates the number of lost pulses of the input clock plus one receiving the input clock, and outputting a first pulse width expanded signal of the input clock having an m+1 pulse width, a circuit outputting a read clock having a second frequency near to the the first frequency and stuffing the read clock, a second frequency divider frequency-dividing the read clock at N to output a second frequency-divided signal, a second pulse width expansion circuit connected to receive n frequency divided pulses from the second frequency divider, where n indicates the number of lost pulses of the read clock plus one, receiving the read clock, and outputting a second width expanded signal of the read clock having an n+1 pulse width; a phase detector outputting a phase detection signal when the phases of both pulse width expanded signals coincide, and a stuffing request circuit outputting a stuffing request signal to the stuffing circuit. The stuffing circuit stuffs the read clock in response to the stuffing request signal.

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Yokohama, Japan

Hirohisa Miyaou