Fujitsu Corporation

Fujitsu Semiconductor Limited

Socionext Inc.

Fujitsu Microelectronics Limited

Other

Fujitsu Vlsi Limited

Hirohisa Matsuki

Kenichi Nagashige

Norio Fukasawa

Mitsutaka Sato

Yuzo Hamanaka

Shigeyuki Maruyama

Muneharu Morioka

Yoshiyuki Yoneda

Eiji Watanabe

Tetsuya Fujisawa

Yoshitaka Aiba

Masamitsu Ikumo

Toshimi Kawahara

Hiroyuki Matsui

Yasuhiro Shinma

Yutaka Makino

Junichi Kasai

Kazuhiro Tashiro

Makoto Haseyama

Koki Otake

Mitsunada Osawa

Tetsurou Honda

Jun Fukuda

Kenichi Kado

Yasuyuki Itoh

Masanori Onodera

Masataka Mizukoshi

Kazuto Tsuji

Toshio Hamano

Yoshihiro Kubota

Masao Sakuma

Kazuyuki Imamura

Tadahiro Okamoto

Osamu Igawa

Takashi Hozumi

Hiroyuki Yoda

Kunio Kodama

Tadahiro Okamato

Takahiro Yurino

Kazuhiko Kobayashi

Masahiro Sugimoto

Eiji Yoshida

Hideharu Sakoda

Masashi Takenaka

Ryuji Nomoto

Shuichi Chiba

Fumihiko Taniguchi

Koju Aoki

Tadashi Uno

Joji Fujimori

Motoshu Miyajima

Shigeki Harada

Takao Ohno

Masahiko Ishiguri

Hiroyuki Sakima

Yoshimi Suzuki

Toshiyuki Kuramochi

Satoshi Terayama

Akiyo Mizutani

Minoru Nakada

Toshiki Yoshida

Tuyosi Sohara

A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.

Semiconductor device and method for manufacturing the same

A semiconductor device (semiconductor module) includes a circuit board (module board) and a semiconductor element mounted on the circuit board. A shielding layer that blocks electromagnetic waves is disposed on the upper surface of the semiconductor element, and an antenna element is disposed over the shielding layer. The semiconductor element and the antenna element are electrically connected to each other by a connecting portion. This structure enables the semiconductor device to be reduced in size and to have both an electromagnetic-wave blocking function and an antenna function.

Semiconductor device having antenna element and method of manufacturing same

A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.

Method of testing a semiconductor device and suctioning a semiconductor device in the wafer state

A reflow apparatus, where formic acid is used for cleaning a surface of a solder electrode on a processing target, is disclosed. The reflow apparatus includes a processing chamber, a formic acid introduction mechanism for supplying an atmosphere gas containing formic acid to the processing chamber, and a shielding member that is made of a material having corrosion resistance against formic acid. The shielding member is arranged between a reflow processing section of the processing chamber and an inner wall of the processing chamber. In place of or in addition to the shielding member, the reflow apparatus may include a heater for decomposing residual formic acid.

Reflow apparatus, a reflow method, and a manufacturing method of a semiconductor device

A semiconductor device and manufacturing method thereof improving moisture resistance of a FeRAM. After a probe test using a pad, a metal film is formed to cover the pad in an opening of a protective film and a region from the pad to an opening outer periphery of the protective film. On the metal film, a metal bump is formed. The metal film is formed to have a two-layer structure of the first and second metal films. Materials of the lower and upper layers are selected mainly in consideration of adhesion to the protective film and adhesion to the metal bump, respectively. Film formation conditions thereof are set to provide metal films with a desired quality and thickness. Thus, penetration of moisture from the pad or the periphery into a ferroelectric capacitor can be prevented and therefore, occurrence of potential inversion abnormalities due to penetrated moisture can be effectively suppressed.

Semiconductor device and manufacturing method thereof

Reflow apparatus, a reflow method, and a manufacturing method of semiconductor device

A semiconductor device, including a semiconductor substrate where a plurality of functional elements is formed; and a multilayer interconnection layer provided over the semiconductor substrate, the multilayer interconnection layer including a wiring layer mutually connecting the plural functional elements and including an interlayer insulation layer, wherein a region where the wiring layer is formed is surrounded by a groove forming part, the groove forming part piercing the multilayer interconnection layer; and the groove forming part is filled with an organic insulation material.

Semiconductor device, manufacturing method of the semiconductor device, and mounting method of the semiconductor device

A semiconductor device includes a first semiconductor chip () having a first terminal () on one surface, a second semiconductor chip () which is larger than the first semiconductor chip () and on which the first semiconductor chip () is stacked and which has a second terminal () on one surface, an insulating layer () formed on a second semiconductor chip () to cover the first semiconductor chip (), a plurality of holes () formed in the insulating layer () on at least a peripheral area of the first semiconductor chip (), a via () formed like a film on inner peripheral surfaces and bottom surfaces of the holes () and connected electrically to the second terminal () of the second semiconductor chip (), a wiring pattern () formed on an upper surface of the insulating layer (), and an external terminal () formed on the wiring pattern ().

Semiconductor device having a plurality of semiconductor chips and method for manufacturing the same

A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.

Method of fabricating semiconductor device

In a manufacturing method of a semiconductor device, a semiconductor substrate having a plurality of semiconductor chips formed on one of principal surfaces of the substrate is cut into the plurality of semiconductor chips through dicing. A first cutting process is formed on one of the principal surfaces of the substrate to produce two cutting grooves between two neighboring ones of the plurality of semiconductor chips, each cutting groove being adjacent to one of the neighboring ones of the plurality of semiconductor chips. A second cutting process is performed on the other of the principal surfaces of the substrate to produce a cutting groove overlapping the two cutting grooves produced by the first cutting process.

Method of dicing a semiconductor substrate into a plurality of semiconductor chips by forming two cutting grooves on one substrate surface and forming one cutting groove on an opposite substrate surface that overlaps the two cutting grooves

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Kawasaki, Japan

Hirohisa Matsuki