Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Hirohisa Machida

Hideki Ando

Takeo Nakabayashi

Shuji Murakami

Harufusa Kondo

Michiru Hori

Hiroyuki Mizutani

Hiroshi Ochi

Hideaki Ando

The present invention provides a standard cell and a scan flip flop circuit capable of introducing a scan test also to a system LSI having an ACS circuit. One standard cell is configured by: a 3-input selection circuit for selecting one signal from three input signals; and a flip flop circuit. The 3-input selection circuit receives a control signal and a test signal at its control input part and its first input part, respectively. First and second signals are supplied to second and third input parts, and a selection signal is supplied to a selector input part. On the basis of the control signal and the selection signal, any of the signals input to the first to third input parts is output from the output part.

Standard cell and semiconductor device

A viterbi decoder includes a viterbi decoding section which decodes input data, and a coding unit which codes the data decoded by the decoding unit. The number of bit error corrections in the output of the coding unit during a measurement period which is set externally are detected. Further, a synchronized state is detected based on the detected number of bit error corrections and a threshold. A threshold detecting unit detects the threshold from the detected number of bit error corrections during a threshold detection period that includes the measurement period.

Viterbi decoder and synchronism controlling method

Following arrangement of an adaptive equalizer with a direct filter structure according to the least mean square error architecture, look ahead conversion of modifying a tap coefficient of the next cycle utilizing the tap coefficient of a predetermined preceding cycle is carried out and then a retiming process of adjusting the timing of tap coefficients and signals is carried out to arrange delay elements, whereby a transposition filter is realized. A high-speed adaptive equalizer is provided that can have the critical path reduced without increasing the hardware amount and that is superior in expansionability.

Adaptive equalizer and designing method thereof

The resampler circuit according to the present invention is arranged such that the number of multiplication, that is, the number of multiplying means is reduced by storing the coefficients in each of the time intervals between the time point at which the time interval T has elapsed and a predetermined time point in a plurality of ROMs, taking advantage of the symmetrical characteristic of the waveform indicated by the SINC function in the direction in which the number of T increments and that in which the number of &minus;T increments, except the time intervals from the reference time 0, namely &lsqb;0, T&rsqb; and &lsqb;0, &minus;T&rsqb;. In addition, the ROM size is also reduced by storing in each ROM the coefficients for only a half of each of the time intervals on the basis of the above symmetrical characteristic.

Resampling method and resampler circuit

To obtain a high performance computer decreased in the number of commands to be executed. A control circuit receives a command (CMD), and outputs a special command signal which becomes 'H' when the command (CMD) instructs 'push' command, to a register file. The register file, when the special command signal is 'H', outputs the stored data value of register as register data regardless of the values of read register address signals, and and outputs the stored data value of register as register data. An ALU adds the register data and control data, and outputs the ALU operation result to the register file. An address adder adds the register data and control data, and outputs the address addition result to an external memory.

Processor using implicit register addressing

A computer of a pipeline type is provided in which a processing of exchanging data stored in two data storing portions can be performed at a high speed by adding a comparatively simple circuit structure without increasing the operation processing time of an instruction executing portion. An exclusive-OR gate executes the exclusive-OR of the ordinary operation result (ALU operation result) on the E-stage stored in an operation result register and data stored in a bus register, and outputs the EXOR operation result to a selector. The selector outputs one of the EXOR operation result and the ALU operation result stored in the operation result register based on SWAP indication information stored in a register for SWAP instructions.

Method for generating an object code for a pipeline computer process to

A TLB circuit includes a memory circuit and a FAC-CAM circuit, a kind of associative memory. The FAC-CAM circuit receives two data entries, and computes a virtual address while comparing the virtual address with prescribed values stored therein. As the result of the comparison, when the prescribed value which is coincident with the virtual address is found, at least one of a group of coincidence signals is activated and a hit signal is outputted. Thus, the associative memory utilizing the FAC circuit enables a high-speed addition operation and comparison.

Associative memory circuit and TLB circuit

A heapsort processor includes a first decoder for selecting a parent macro cell and a second decoder for selecting macro cell pair 480 having twice or twice plus one the address of the parent. The data of the parent is read to the first bit line, while data of a macro cell storing larger data in macro cell pair is read to the second bit line. The processor further includes a circuit for exchanging, when the data on the second bit line is larger than the data on the first bit line, the data of these bit lines and for writing the exchanged data to original macro cells. This enables generation of heap data. When a macro cell storing a root is selected by disabling the second decoder, part of a heapsort algorithm can be implemented in a hardware.

Processor circuit for heapsorting

Disclosed is a sorting apparatus for sorting applied n data. Data to be sorted are once held within data registers. Odd-numbered comparison/exchange circuits and even-numbered comparison/exchange circuits are alternately enabled, so that two data held between adjacent two data registers are compared/exchanged. Comparison/exchange circuits apply signals indicating data exchange to a sorting completion detecting circuit. Since sorting completion detecting circuit detects completion of sorting in response to the applied exchange signal, an operation after the completion of sorting is stopped. That is, a processing in the sorting apparatus ends in a short time.

Data sorting apparatus capable of detecting completion of data sorting

A semiconductor integrated circuit device designed with CAD is formed of a plurality of standard cells including at least four I/O terminals. Each standard cell includes a metal interconnection for a power supply and a metal interconnection for the ground, and also includes an active element formation region and a metal interconnection layer isolated from respective interconnection layers and coupled to a plurality of I/O terminals at a position above it. If it is desired to use the metal interconnection as a power signal line, a via hole is formed in an insulator film, and the metal interconnection layer and the metal interconnection for the power supply are coupled together therethrough.

Standard cells interconnection structure including a modified standard

An associative memory system using an associative memory circuit, capable of performing hit judgment on cache data at a high speed. The associative memory system comprises a virtual-address holding CAM circuit 2 for outputting a hit signal 5 when the data previously stored in a supplied address coincides with a supplied virtual address 4, a cache-tag memory circuit 1 for outputting cache-tag data coinciding with the supplied virtual address 4 when the data is present, and a physical-address holding CAM circuit 3 which connects with an output line for outputting the hit signal 5 given from the CAM circuit 2 and outputs the hit signal 6 when a physical address previously stored in the memory area from which the hit signal is outputted coincides with cache tag data supplied from the cache-tag memory circuit 1.

Associative memory system for performing hit judgment on cache data

The multiplier includes a register circuit for holding a multiplicand X, a multiplier register circuit for holding a multiplier Y, a second order Booth decoder circuit for decoding prescribed less significant bits of the multiplier Y according to the second Booth algorithm, and a third order Booth decode circuit for decoding more significant bits of the multiplier Y according to the third Booth algorithm. A tripled of the multiplicand X is produced in a 3X producing circuit in parallel with a multiplication operation utilizing the second Booth algorithm in an adder array. The output of adder array together with the output of 3X producing circuit is applied to an adder array for executing a multiplication operation according to the third order Booth algorithm. Production of an odd number multiple data of the multiplicand necessary for the third order Booth algorithm is executed in parallel with the multiplication operation according to the second order Booth algorithm, and therefore time required for producing the triple can apparently be eliminated. Thus, a multiplier capable of executing multiplication at a high speed in a hardware manner is provided.

Hardware implemented multiplier for performing multiplication of two

An address translator has an improved data comparison circuit for comparing two pieces of data having n bits, e.g., 12 bits. In the data comparison circuit, cell circuits compare two pieces of data for every corresponding 4 bits. When a match is detected in the comparison of a set of 4 bits, a signal representative of the comparison result of the lower-order bits is bypassed. Hence, delay of signal propagation which may occur in the cell circuit in which the match is detected is reduced.

Address translator having a high speed data comparator

A content addressable memory circuit includes a plurality of CAM cell circuits provided in a matrix of rows and columns, a matching line arranged corresponding to each row, and a rewrite control circuit for generating a rewrite instruct signal according to a signal on the matching line. The CAM cell circuit includes a master memory portion for storing a reference data to be compared, a slave memory portion for storing data of an adjacent word, transfer element for transferring to the master memory portion the data stored in the slave memory portion according to a rewrite instruct signal from the rewrite control circuit, and a comparison/driving portion for comparing an input data transmitted to a bit line with the data stored in the master memory portion to drive an associated matching line according to the comparison result. The stored data in the CAM cell circuit is updated according to a shifting operation. The input data is stored in the CAM cell circuit of a certain address. The least recently accessed data is always stored in the CAM cell circuit of another certain address. A content addressable memory circuit is obtained that executes LRU algorithm at a high speed.

Content addressable memory cell and content addressable memory circuit

A semiconductor memory device 1 includes a plurality of memory circuits 10. Each of the memory circuits 10 includes a data bit memory cell 11, a sign bit memory cell 12, a converting circuit 13 and a selecting circuit 14. The data bit memory cell 11 stores one bit of binary number data or a data bit of redundant binary number data. The sign bit memory cell 12 stores a digit of a sign bit of redundant binary number data. The converting circuit 13 converts redundant binary number data into binary number data on the basis of the data bit stored in the data bit memory cell and the sign bit stored in the sign bit memory cell 12. The selecting circuit 14 selects the data bit stored in data bit memory cell 11 or the one bit of binary number data outputted by the converting circuit 13.

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Hyogo, Japan

Hirohisa Machida