Kabushiki Kaisha Toshiba

Hirohisa Iizuka

Riichiro Shirota

Hiroaki Hazama

Seiichi Aritome

Naoki Koido

Kazuhiro Shimizu

Akira Goda

Kazuhito Narita

Wakako Moriyama

Fumitaka Arai

Seiichi Mori

Tadashi Iguchi

Hiroaki Tsunoda

Norihisa Arai

Eiji Kamiya

Shinji Satoh

Norio Ohtani

Tohru Maruyama

Takuya Nakamura

Katsuhiro Ishida

Naoki Kai

Kunihiro Terasaka

Norio Ootani

A semiconductor device comprises a non-volatile memory including a memory cell array, element isolating regions, a second trench and a word line. The memory cell array is constituted by memory cells which have floating electrodes and are arranged in the shape of a matrix on a semiconductor substrate. Each of the element isolating regions has a first trench formed in the semiconductor substrate and between memory cells adjacent to each other along a gate width direction, and an isolating filler filled in the first trench. The second trench is formed in the isolating filler and between the floating electrodes of the memory cells adjacent to each other along the gate width direction, and is narrow at the bottom thereof. The word line is connected to the memory cells, buried in the second trenches and extending along the gate width direction.

Semiconductor memory preventing an electric short circuit between a word line and a semiconductor substrate, and manufacturing method for the semiconductor memory

A semiconductor device includes a plurality of a word lines. The word lines have a set of odd word lines and a set of even word lines. The odd and the even word lines are located from a first end region to a second end region through the cell region located between the first and the second end regions. The odd word lines are divided in the first end region and the even word lines are divided in the second end region to form dummy word line portions.

Semiconductor device and method of manufacturing the same

A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.

Nonvolatile semiconductor memory device and method for manufacturing the same

A method of fabricating a semiconductor device includes forming on a semiconductor substrate a gate electrode with a gate insulating film being interposed between the substrate and the electrode, forming an insulating film for element isolation protruding from a surface of the semiconductor substrate, forming an oxide film on the surface of the semiconductor substrate with the gate electrode and the element isolation insulating film having been formed, removing the oxide film in a region in which a self-aligned contact hole is to be formed while using a resist pattern for removing the oxide film formed in a region in which the self-aligned contact hole is formed, and etching a part of the element isolation insulating film protruding from the surface of the semiconductor substrate so that said part is substantially on a level with the surface of the semiconductor substrate, while using the resist pattern for removing the oxide film formed in the region in which the self-aligned contact hole is formed.

Method of fabricating semiconductor device

A nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit comprises a semiconductor substrate, isolation insulating films for defining a plurality of element formation regions, each of the isolation insulating films being buried in an isolation trench provided in the semiconductor substrate, a floating gate provided in each of the element formation regions via a first gate insulating film, a control gate provided on the floating gate via a second gate insulating film, and source and drain regions provided in the semiconductor substrate in self-alignment with the control gate, wherein the floating gate is self-aligned at an isolation end in a direction of a channel width, and comprises a plurality of polysilicon films.

Nonvolatile semiconductor memory device and manufacturing method therefor

A non-volatile semiconductor memory device includes a plurality of bit lines, a bit line contact corresponding to the bit lines, a first NAND string and a second NAND string, a first string selective transistor and a second string selective transistor, and a third string selective transistor and a fourth string selective transistor. The first and third string selective transistors are connected to each other, whereas the second and fourth string selective transistors are connected to each other. Each of the first and fourth string selective transistors has a first gate length and each of the second and third string selective transistors has a second gate length differing from the first gate length.

Semiconductor device provided with NAND strings and select gates having different gate lengths

A method of fabricating a semiconductor device includes forming a resist pattern so that an opening between select gates of a select gate transistor is formed in a memory cell region, implanting threshold-adjusting ions under the select gate with the resist pattern serving as a mask and removing an oxide film, forming a nitride film and an interlayer insulation film after the resist pattern has been removed, forming a resist pattern used to form a contact hole between the select gates and a contact hole for a transistor to be formed in the peripheral circuit region, the transistor having a higher breakdown voltage than a memory cell transistor and etching the interlayer insulation film, the nitride film and the gate insulation film individually with the resist pattern serving as a mask.

A nonvolatile semiconductor memory device includes a memory cell array region including a plurality of NAND cells, each NAND cell having a plurality of memory cell transistors, and which are arranged in series, and a plurality of select transistors. A trench-type isolation region is formed between columns in the array of the NAND columns. The trench-type isolation region is formed in self-alignment with end portions of the channel region and a floating gate of the memory cell transistor, formed in self-alignment with the end portion of a channel region of the select transistor, and has a recess formed in at least the upper surface between the floating gates of the memory cell transistors.

Nonvolatile semiconductor memory device having trench-type isolation region, and method of fabricating the same

A nonvolatile semiconductor memory device includes erasable and programmable memory cell transistors, a selection transistor, a peripheral transistor, first post-oxidation films each provided on a gate electrode of all of the plurality of erasable and programmable memory cell transistors, a second post-oxidation film provided on a gate electrode of the selection transistor, a third post-oxidation film provided on a gate electrode of the peripheral transistor, and an insulating film covering the memory cell transistors, the selection transistor, and the peripheral transistor. The insulating film is harder for an oxidizing agent to pass through than a silicon oxide film. The insulating film has an oxidized region. The insulating film includes a silicon nitride film. The oxidized region is provided in a surface of the silicon nitride film.

A nonvolatile semiconductor memory device includes comprises: an element isolation region being in contact with a first element region, an insulating film covering a memory cell, a peripheral transistor and the element isolation region, an inter-level insulating film provided on the surface of the insulating film, and a contact hole provided in the inter-level insulating film and the insulating film. The inter-level insulating film contains an insulator different from the insulating film. The contact hole reaches at least one of source and drain diffusion layers of the memory cell and overlaps the element isolation region. The insulating film contains an insulator different from the element isolation region and the insulating film is harder for an oxidizing agent to pass therethrough than a silicon oxide film. A surface of the insulating film is oxidized.

Nonvolatile semiconductor memory device covered with insulating film which is hard for an oxidizing agent to pass therethrough

A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.

Semiconductor device

In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.

A nonvolatile semiconductor memory device includes memory cell transistors, peripheral transistors, first post-oxidation films provided on the gate electrode of all of the memory cell transistors, second post-oxidation films provided on the gate electrode of all of the peripheral transistors, first insulating films provided on the first post-oxidation films and covering a side surface of the gate electrode of all of the memory cell transistors and second insulating films provided on the second post-oxidation films and covering a side surface of the gate electrode of all of the peripheral transistors. The first and second insulating films are harder for an oxidizing agent to pass therethrough than a silicon oxide film, and the first and second insulating films are oxidized.

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Yokohama, Japan

Hirohisa Iizuka