Hitachi Ulsi Systems Co., Ltd.

Other

Renesas Electronics Corporation

Renesas Technology Corp.

Hitachi, Ltd.

Renesas Northern Japan Semiconductor, Inc.

Hirohiko Yamamoto

Kenichi Kuroda

Kozo Watanabe

Akira Takamatsu

Shuji Ikeda

Hideo Miura

Norio Suzuki

Yasuko Yoshida

Kazushi Fukuda

Shinichi Horibe

Masamichi Kobayashi

Hirofumi Shimizu

Yasushi Matsuda

Toshio Nozoe

Norio Ishitsuka

Tadanori Yoshida

Ryouichi Furukawa

Masayuki Ishizaka

Yuzuru Ohji

Kazuyuki Suko

Yasuhiro Sugawara

Maki Shimoda

Koichi Saitoh

Masayuki Hiranuma

Shinpei Iljima

Toshio Uemura

Hiroaki Kikuchi

Toshiaki Sawada

A semiconductor device includes grooves defining an active region, including a MISFET, and dummy regions. A first interlayer insulation film is formed over the MISFET, the active region and the dummy regions. A first wiring, and first and second dummy wirings are formed over the first interlayer insulation film. A second interlayer insulation film is formed over the first wiring and the dummy wirings. The second dummy wirings are arranged between the first wiring and the first dummy wirings, and the pitch of the first dummy wirings is larger than that of the second dummy wirings. In planar view, the first and second dummy wirings are arranged over the dummy regions, and the size of each of the first dummy wirings is larger than size of each of the second dummy wirings. The first wiring and the first and second dummy wirings are formed of copper as a major component.

Semiconductor device and a method of manufacturing the same and designing the same

There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DPof relatively wider area and the second dummy pattern DPof relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DPoccupy a relatively wide region among the dummy region FA.

Method of manufacturing a semiconductor device including dummy regions and dummy wirings

Semiconductor device having active region and dummy wirings

Method of manufacturing a semiconductor device having an active region and dummy patterns

A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Semiconductor device and process for producing the same

Upon formation of an impurity-added silicon film by a low-pressure CVD apparatus, diffusion of an impurity from another similar silicon film, which has already been formed over the inside walls of the deposition chamber, is suppressed in the following manner. After insertion of a semiconductor substrate, having a gate oxide film (insulating film) formed thereover, into the deposition chamber of a CVD apparatus (first film forming apparatus), the inside of the deposition chamber is heated while minimizing, relative to a time A required for heating of the inside of the deposition chamber under atmospheric pressure, a time B required for the subsequent heating in the deposition chamber under a pressure adjusted to vacuum or not greater than atmospheric pressure. The formation of an impurity-added silicon film is then started. At this time, the relation between A and B is controlled to satisfy the following equation: 0.1&#xd7;B&#x2266;A&#x2266;13&#xd7;B.

Fabrication method of semiconductor integrated circuit device

Conductive layers are formed in the trenches made in an insulating film in the following manner. First, an amorphous silicon film A is deposited in the trenches made in a silicon oxide film . A photoresist film is then formed on the amorphous silicon film A by means of spin coating. Then, exposure light is applied to the entire surface of the photoresist film , thereby exposing to light those parts of the photoresist film which lie outside the trenches . The other parts of the photoresist film , which lie in the trenches are not exposed to light because the light reaching them is inadequate. Further, the photoresist film is developed thereby removing those parts of the film which lie outside the trenches and which have been exposed to light. Thereafter, those parts of the amorphous silicon film A, which lie outside the trenches , are removed by means of dry etching using, as a mask, the unexposed parts of the photoresist film which remain in the trenches

Method of forming a data-storing capacitive element made in an insulating film on a semiconductor substrate

A first silicon film is so formed as to extend along the inner surface of trenches formed in a silicon oxide film , an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode of a capacitance device can be lowered.

HSG semiconductor capacitor with migration inhibition layer

Growing community of inventors

Hachioji, Japan

Hirohiko Yamamoto