Sharp Kabushiki Kaisha Corporation

Hirohide Nakagawa

Isamu Haneda

Isamu Washizuka

Kosuke Nishimura

Shintaro Hashimoto

Toshio Nishimura

Shintarou Hashimoto

A new and useful combination of a radio receiver, a television receiver, a tape recorder and an electronic calculator is described. A display (for example, a cathode ray tube) of the television receiver is connected to serve also as a display for the electronic calculator. Data may be introduced into the calculator via the tape recorder and recorded into the tape recorder. The television receiver serves a display and the tape recorder serves as an external storage, with respect to the calculator.

Combined television receiver/tape recorder/calculator

A combined home-use-television set/calculator electronic system comprising a control unit for conducting arithmetic calculations and for displaying calculation results on an image screen of the home-use-television set. A keyboard unit is exchangeably connected to the control unit for increasing operation abilities of the combined home-use-television set/calculator electronic system. A read only memory cartridge is exchangeably secured to the control unit. A read only memory corresponding to a selected keyboard unit is secured to the control unit for developing operation instruction signals which are required for performing the arithmetic calculations associated with the selected keyboard unit.

Television set/calculator interface including exchangeable keyboard

A combined timekeeper and calculator implemented on an LSI semiconductor chip includes a generator stage for generating basic clock signals and system clock signals which are obtainable by modifying the basic clock signals, and a processor stage responsive to the supply of the system clock signals for performing the operations required for the timekeeper mode and calculator mode. The basic clock signals also are modified to create second signals useful in the timekeeper mode. The generator to supply the processor unit with the system clock signals while the second signal is being generated. Upon completing the operations by the processor unit, a clock control circuit prevents the processor unit from being supplied with the system clock signals.

Combined timekeeper and calculator with low power consumption features

The present disclosure is directed toward a system for driving a plurality of liquid crystal display units each having a common electrode, a plurality of segment electrodes and a liquid crystal composition interposed between the said electrodes. First, second and third voltage levels are determined with respect to a reference level in such a manner that a voltage difference between any possible combinations and the reference level except the combination of the third level and the reference level is not higher than a given threshold voltage which initiates enabling of the liquid crystal display units. When the liquid crystal display units are desired to be energized, signals of the reference level and the third level are alternatively applied to the common electrode, whereas the inversion thereof is applied to the segment electrodes. When the liquid crystal display units are desired to be disabled, a signal either of the first or second level is applied to at least one of said electrodes.

CMOS drive system for liquid crystal display units

A general-purpose LSI (large-scale integrated circuit) computation circuit provides segment signals of high frequency at respective ones of its output terminals for displaying the computation results. It is necessary to provide a pulse frequency and pulse width converter in order to adapt the segment signals from the computation circuit to a form compatible with liquid crystal display units. There are provided flip-flops and normally closed switches for feeding the output signals of the flip-flops back to the input terminals of the flip-flops in order to temporarily maintain the segment signals within the converter. The input terminals of the flip-flops are connected with the respective ones of the output terminals of the computation circuit through normally open switches. The input terminals of the flip-flops are also connected with the respective segment electrodes of the liquid crystal display units. Synchronization between closing of the normally open switches and opening of the normally closed switches enables updating of the contents of the flip-flops, thereby achieving the reduction of the necessary number of terminals for the converter.

Information storage and frequency converter for liquid crystal display

An improvement on a display system which displays multi-digit numeral information on a time-shared basis in response to application of bipolarity alternating voltage to liquid crystal display units. Each of the liquid crystal display units has a common electrode actuated by one of sequentially phase-shifted timing signals and a predetermined number of segment electrodes actuated by segment signals of which combinations are representative of the multi-digit numeral information to be displayed. Particularly, in the present system, visual display is provided over successive repetition of first and second display cycles in a manner that timing selection for the respective common electrodes is effected with one polarity or phase during the first display cycle and subsequently timing selection for the same is effected with the opposite polarity or phase during the second display cycle. This provides a considerable improvement in life time and immunity from blinking information caused due to the decreasing of display frequency.

Growing community of inventors

Sakurai, Japan

Hirohide Nakagawa