Seiko Epson Corporation

Kabushiki Kaisha Suwa Seikosha

Hirofumi Yasuda

Kazuo Tanaka

Toshihiko Kondo

Akira Uematsu

A semiconductor device includes a substrate, a first insulating film carried on the substrate, a first conductor layer having sides and carried on the first insulting film, and an interlayer insulating film overlying the first conductor layer and the first insulating film. The interlayer insulating film includes a top portion which overlies the first conductor layer and a pair of sidewall portions which overlie the first insulating film and are adjacent to and in contact with the sides of the first conductor layer. The semiconductor also includes a second conductor layer which extends from overlying part of the top portion of the interlayer insulating film to and in contact with an exposed portion of the substrate and adjacent the first insulating film wherein a portion of the second conductor layer is in contact with a thinned portion of the interlayer insulating film.

Semiconductor device having an inter-layer insulating film disposed

A semiconductor memory device for reading data from a selected memory cell. The memory cells are arranged in an array. First bit lines and word lines, coupled to the memory cells, are arranged in a matrix. The word lines select the selected cell. An amplification circuit amplifies the current passing through the selected memory cell and is coupled to the first bit line. A second bit line is coupled to the amplification circuit and carries the amplified current. A sensing circuit coupled to the second bit line senses the current on the second bit line. As a result, the current passing through the selected memory cell is detected.

Semiconductor memory device

A semiconductor memory device for reading data from a selected memory cell. The memory cells are arranged in an array. First bit lines and word lines, coupled to the memory cells, are arranged in a matrix. The word lines select the selected cell. An amplification circuit amplifies the current passing through the selected memory cell and is coupled to the first bit. A second bit line is coupled to the amplification circuit and carries the amplified current. A sensing circuit coupled to the second bit line senses the current on the second bit line. As a result, the current passing through the selected memory cell is detected.

Sense amplifier for semiconductor memory device

A semiconductor device includes a substrate, first insulating film carried on the substrate, first wiring layer carried on the first insulating film and an interlayer insulating film overlying the first wiring layer and first insulating film. The interlayer insulating film has a top portion overlying the first wiring layer and a pair of sidewall portions. The sidewall portions of the interlayer insulating film overlie the first insulating film and the sides of the first wiring layer. The sidewall portions have progressively increasing width in progressing towards the substrate. The device also includes a second wiring layer which extends from overlying part of the top portion of the interlayer insulating film to and in contact with an exposed portion of the substrate adjacent to the first insulating film.

A semiconductor memory device for reading stored data from a selected memory cell in the semiconductor device to a sensing amplifier. An array of memory cells is arranged in a matrix, each memory cell including a MOS transistor. Word lines are organized to select groups of the MOS transistors. A plurality of first bit lines are arrayed in a matrix with the word lines. The word lines and bit lines together select the selected memory cell from the array. Each first bit line is coupled to either the source electrode or drain electrode of a plurality of MOS transistors. There is at least one second bit line. Each second bit line is selectively coupled to at least two corresponding first bit lines. A first bit line selection circuit selectively couples one of the first bit lines to a corresponding second bit line. A first power source line is coupled to the other of the source and drain of the array of the MOS transistors. A second bit line select means selectively couples a second bit line to the sensing amplifier.

An electronic timepiece wherein the timekeeping circuitry utilizes semiconductor-insulating substrate integrated circuitry for effecting high frequency operation is provided. The timepiece includes an oscillator circuit adapted to produce a high frequency time standard signal and is comprised of at least one inverter stage coupled to a high frequency time standard. A divider circuit formed of a plurality of series-connected divider stages produces a low frequency timekeeping signal in response to the high frequency time standard signal being applied thereto. A display is provided for displaying time in response to the timekeeping signal being applied thereto. The oscillator circuit, divider circuit and display include integrated circuit elements and at least the inverter stage of the oscillator circuit includes at least one complementary coupled pair of P-channel and N-channel conductive field-effect transistors having a semiconductor-insulating substrate construction.

Growing community of inventors

Suwa, Japan

Hirofumi Yasuda