Icom Incorporated

Hirofumi Yamauchi

Weimin Sun

Michio Nakajima

The object of the invention is to provide a technique of preventing the limit cycle, with a simplified structure, for the IIR digital filter adopting arithmetic operation part of finite word length. A digital filter shown in FIG. 1 includes an extracting means,to extract only 2 bits at a low end of an input signal S,and to output the extracted signal; an amplifying means,to amplify the extracted signal at an amplitude level to a level larger than a critical input level of an IIR digital filter,and output the extracted signal as amplified; and an adding means,to add the input signal S,and the extracted signal S,as amplified and input them into the IIR digital filter

Digital filter

An input analog signal is sampled at a sampling frequency f.sub.s, which is four times a carrier frequency f.sub.c. A demultiplexer 11 outputs supplied data to four systems sequentially, and generates four zero carriers whose frequencies and amplitudes are equal to each other, with only the phases being different. The delay circuits 12 to 15 delay each one of the zero carriers, and supply delayed signals to adaptive filters 16 to 19. Data output from the four adaptive filters 16 to 19 are selected by a multiplexer 22, and the multiplexer 22 outputs the selected signals as a single signal. The difference between a first zero carrier and an output signals of the first adaptive filter 16 is obtained, and tap coefficients of the adaptive filters 16 to 19 are controlled in accordance with an LMS algorithm based on the difference. A signal output by the multiplexer 22 is output as a reproduced carrier.

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Kitakatsuragi-gun, Japan

Hirofumi Yamauchi