Other

Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Renesas Technology Corp.

Hirofumi Shimizu

Norio Suzuki

Yasushi Matsuda

Shuji Ikeda

Hideo Miura

Yasuko Yoshida

Hirohiko Yamamoto

Akira Takamatsu

Kazushi Fukuda

Shinichi Horibe

Masamichi Kobayashi

Toshio Nozoe

Norio Ishitsuka

Shigeru Matsui

Kazuo Takeda

Makoto Ohkura

Muneo Maeshima

Atsuyoshi Koike

Seiichi Isomae

Hisashi Maejima

Akira Yoshinaka

Yoshimitsu Sugita

Kyoko Minowa

Tomomi Sato

Akira Kanai

A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Semiconductor device and process for producing the same

A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Semiconductor device and process for producing the sme

A defect assessing apparatus and method and a semiconductor manufacturing method for revealing the relationship between the size and depth of defects is disclosed. A detecting optical system is provided for detecting the intensity of scattered light from a defect generated by the shorter wavelength one of the light rays of at least two different wavelengths emitted from irradiating optical systems and that of scattered light from the defect generated by the longer wavelength one of same. A calculating means is provided for determining, from the scattered light intensity derived from the shorter wavelength ray and that derived form the longer wavelength ray, both detected by the detecting optical system, a value corresponding to the defect size and another value corresponding to the defect depth. A display means is provided for displaying a distribution revealing the relationship between defect size and defect depth on the basis of the value corresponding to the defect size and the value corresponding to the defect depth, both determined by the calculating means.

Defect assessing apparatus and method, and semiconductor manufacturing method

In a process for the fabrication of a semiconductor integrated circuit using a double-side mirror-polished wafer or the like, at the portion of a notch,of a notched wafer,a chamfered angle &thgr;,of the first chamfered portion,formed at the inner periphery of the first primary surface,is set smaller than the chamfered angle &thgr;,of the second notch chamfered portion,of the second primary surface,and the chamfered width L,is set larger than the chamfered width L,, whereby the obverse and reverse of the wafer are discriminated by optically discriminating the first notch chamfered portion and the second notch chamfered portion using reflected light, thereby making it certain to fabricate IC on the surface of the wafer and to use the reverse for its handling. The plane view of the notch in the circumferential direction can be maintained symmetrical so that the lowering in the symmetry of the wafer and the number of the IC available from the wafer can be prevented and the standards of the notch can be maintained.

Process for fabrication of semiconductor device, semiconductor wafer for use in the process and process for the preparation of the wafer

A silicon oxide film 2 which is exposed from a side wall of a groove 4a is etched to displace the silicon oxide film 2 backward toward an active region. The displacement amount is set to be equal to or more than a film thickness (Tr) of a silicon oxide film 5 to be formed on an inner wall of the groove 4a in a later thermal oxidation step and equal to or less than twice the film thickness (Tr) thereof. A shoulder portion of the groove 4a can be rounded by a low-temperature heat treatment at 1000.degree. C. or less, by controlling a heat treatment period such that the film thickness (Tr) of the silicon oxide film 5 is more than the film thickness (Tp) of the silicon oxide film 2 and equal to or less than three times the film thickness (Tr) thereof (Tp&lt;Tr.ltoreq.3Tp)

Method of manufacturing a semiconductor integrated circuit device

In a method of making a semiconductor device, a semiconductor wafer having a stacking fault originally contained in the wafer or produced in the wafer through the thermal oxidation of the wafer surface is subjected to an annealing treatment in a non-oxidative atmosphere to eliminate the stacking fault. A PN junction is thereafter formed in an area of the wafer from which the stacking fault is eliminated.

Method of making semiconductor device with PN junction in stacking-fault

Growing community of inventors

Yamanashi, Japan

Hirofumi Shimizu