Denso Corporation

So-ken Corporation

Hirofumi Isomura

Takuya Honda

Tomohisa Kishigami

Hiroyuki Mori

Takuya Harada

Kenji Ito

Takamoto Watanabe

Masakiyo Horie

Toshikazu Hioki

Soichiro Arai

Housyo Yukawa

Yuki Horii

Fumitaka Sugimoto

Yasuhiro Mori

Takeshi Iwai

A ringing suppression circuit is provided at one or more nodes each having a communication circuit executing communication with another node by transmitting a differential signal through a pair of communication lines connected to the nodes. The circuit includes a suppression circuit and an operation mode controller: The suppression circuit is configured to execute a suppression operation for suppressing ringing in the differential signal. The operation mode controller is configured to set an operation mode of the suppression circuit to one of: a normal operation mode, which enables the suppression circuit to execute the suppression operation in response to detecting a change in a level of the differential signal, and a permanent off mode, which disables the suppression circuit to execute the suppression operation on a steady basis.

Ringing suppression circuit

A ringing suppression circuit connected to a transmission line to suppress ringing caused by the transmission line transmitting a differential signal using a pair of signal lines, the differential signal varying between a high level and a low level, the pair of signal lines including a high potential signal line and a low potential signal line, the ringing suppression circuit including: an inter-line switching element that is connected between the pair of signal lines; a control portion that performs a ringing suppression operation in response to detecting a level change in the differential signal, wherein the ringing suppression operation turns on the inter-line switching element to decrease an impedance between the pair of signal lines; and a suppression operation prohibiting portion that prohibits the control portion from performing the ringing suppression operation in response to detecting a signal caused by a signal on the transmission line.

Ringing suppression circuit and ringing suppression method

A ringing suppression circuit is provided at a node having a communication circuit executing communication with another node by transmitting a differential signal through a pair of communication lines. The ringing suppression circuit includes: a suppressor configured to perform a suppression operation to suppress ringing occurred with a transmission of the differential signal by connecting a resistive component between the pair of communication lines; and a reference potential provider configured to provide a reference potential, which corresponds to a midpoint potential of the pair of communication lines during a steady state, to an intermediate point of the resistive component.

A ringing suppression circuit is provided at one or more nodes each having a communication circuit executing communication with another node by transmitting a differential signal through a pair of communication lines connected to the nodes. The operation controller is configured to shift a mode of the suppressor to a normal-operation mode when the differential signal is transmitted through the pair of communication lines, and to shift the mode of the suppressor to a low-current operation mode when the differential signal is not transmitted through the pair of communication line. A current consumption of the suppressor is less in the low-current operation mode than the normal-operation mode. The suppressor and the operation controller are configured to receive permanent power from a DC power supply, and the communication circuit is configured to receive power from the DC power supply via a power supply switch.

A communication node is connected to a transmission line which transmits a differential signal changeable between a high level and a low level and has a high potential signal line and a low potential signal line as a pair of signal lines. The communication node includes: an inter-line potential detector that detects an intermediate potential between the pair of signal lines; a node potential detector that detects an intermediate potential of an operation power source voltage which is supplied to the communication node; and a voltage adjuster that detects a difference between the intermediate potential detected by the inter-line potential detector and the intermediate potential detected by the node potential detector, and adjusts the operation power source voltage in accordance with the difference.

Communication node

A ringing suppression circuit, which is connected to a transmission line for transmitting a differential signal changeable between a high level and a low level in a binary level through a pair of a high potential side signal line and a low potential side signal line, and suppresses ringing that occurs in association with transmission of the differential signal, includes: an inter-line switching element that is connected to the pair of the high potential side signal line and the low potential side signal line; and a control unit that turns on the inter-line switching element and fixes an on state when detecting that the differential signal changes from the high level to the low level, and releases the on state after a predetermined time is measured and elapsed.

A ringing suppression circuit includes: a single line switching element, which is driven by a voltage, that is connected between a pair of signal lines; a controller that detects a change in a level of the differential signal and turns on the single line switching element to lower an impedance between the pair of signal lines; a period detector that detects a length of a suppressing period indicated by a setting signal, which is an input; and a suppressing period storage that stores the length of the suppressing period which is detected by the period detector. In addition, the pair of signal lines includes a high potential signal line and a low potential signal line. Moreover, the controller turns on the single line switching element for only the suppressing period having the length, which is stored in the suppressing period storage.

An input part is supplied with a low voltage from a low voltage power supply line. A level shift part and an output part are supplied with a high voltage from a high voltage power supply line. An input terminal is pulled up by a resistor and connected to the level shift part through a buffer circuit and an inverter circuit. The level shift part is connected in series with an NMOS and turned on when the input terminal changes to a low level. The output terminal is pulled up by a resistor through the buffer circuit. Even when the level shift part operates unstably because of long delay time from rising of a potential of the high voltage power supply line to rising of a potential of the low voltage power supply line, the output voltage is maintained at a high level.

Level shift circuit

The present invention provides, as one aspect, a control system having sensor units and an electronic control unit. The electronic control unit includes a transmission controlling means which sets a signal line connected to the sensor unit, which is a destination of communication data, to a first state, sets the signal line connected to the sensor unit, which is not the destination, to a second state, and transmits the communication data to the destination via a communication line. The sensor unit includes a reception controlling means which determines a state of the signal line connecting a sensor to the electronic control unit. When determining that the signal line of the sensor unit is in the first state, the reception controlling means receives the communication data and performs a predetermined process. When determining that the signal line is in the second state, the reception controlling means discards the communication data.

Control system, electronic control unit, and communication method

A reference voltage and an input signal voltage are applied to gates of FETs each equipped with a LOCOS-drain structure, respectively, and currents according to the voltages are made to flow from a power supply voltage Vbat to drain sides through resistors and sources, respectively. The currents are made to flow in FETs to be converted to voltages. Then, both voltages are compared in a comparator. When a potential of a reference voltage input terminal in the comparator that operates with power provided by a power supply Vcc tends to rise above a predetermined level, a FET is turned on and clamps the voltage so as to suppress its potential rise.

Comparator circuit

A voltage-to-time conversion circuit compares a ramp-wave voltage, which steps up at a certain gradient, with each of a reference voltage, an input voltage, and a reference voltage, and produces a PB pulsating signal representing the times which the voltages require for having a predetermined relationship to the ramp-wave voltage. An encoder circuit converts the times into coded data items according to the ratios of the times to a common unit time. A normalization circuit determines a conversion characteristic curve on the basis of the coded data items, into which the times required by the reference voltages are converted, and A/D-converted values predefined for the reference voltages, and fits the coded data, into which the time required by the input voltage is converted, to the characteristic curve. Thus, the A/D-converted value of the input voltage Vin is calculated.

A/D converter

A semiconductor integrated circuit device is provided to reduce the adverse effect of PWM noise occurring in a PWM driving section on an analog voltage processing section in an IC, in which digital and analog circuits are combined on a single chip. A sampling signal generation circuit outputs a sampling signal St to an A/D converter at a predetermined time when 'delay time td+allowance time ta' has elapsed from a start signal Sp. The delay time td is shorter than 'the minimum time width of H level of PWM signal SPWM&#x2212;allowance time ta'. The delay time td is also time from the variation of level of the PWM signal SPWMto actual variation in the passage of current through a power section.

Semiconductor integrated circuit device having a sampling signal generation circuit

In a clock-synchronized serial communication device, a counter counts pulses in a communication clock signal. When the count reaches 8, the counter sets a start signal. With this start signal, a pulse generator outputs the first to fourth signals successively. Received data stored in a receiving shift register is transferred to a received-data processing circuit synchronously with the first signal. The received data is further transferred to a timer-setting value register as a timer-setting value synchronously with the second signal. A timer present value is output from a timer present value register synchronously with the third signal. The timer present value is further written into a transmitting shift register as transmission data synchronously with the fourth signal.

Clock-synchronized serial communication device and semiconductor integrated circuit device

A data conversion device for converting analog data to digital data, or digital data to analog data, is composed of a data converter. and a mediator. Plural data groups are fed to the data converter that coverts the data, group by group, upon receipt of a request for converting a particular data group. If plural requests are simultaneously made, the mediator makes mediation among the plural requests to select a data group to be first converted and to set a priority order. A function uniquely corresponding to a combination of the plural requests is generated in the mediator, and the mediation is performed based on the generated function with reference to a preinstalled table showing a relation between the function and the request to be selected.

Data conversion device having mediator for determining data conversion order

A buffer circuit includes a signal input terminal and a signal output terminal. A first operational amplifier includes a differential amplifier circuit having an input transistor of an N-channel MOS type. The first operational amplifier has an inverting input terminal and an output terminal connected to each other. The first operational amplifier has a non-inverting input terminal connected to the signal input terminal. A second operational amplifier includes a differential amplifier circuit having an input transistor of a P-channel MOS type. The second operational amplifier has an inverting input terminal and an output terminal connected to each other. The second operational amplifier has a non-inverting input terminal connected to the signal input terminal. A first switching device operates for connecting the output terminal of the first operational amplifier to the signal output terminal when a voltage of an input signal applied to the signal input terminal is in a range where the first operational amplifier is operative. A second switching device operates for connecting the output terminal of the second operational amplifier to the signal output terminal when the voltage of the input signal applied to the signal input terminal is in a range where the second operational amplifier is operative.

Growing community of inventors

Kariya, Japan

Hirofumi Isomura