Kabushiki Kaisha Toshiba

Hirobumi Matsuki

Takahiro Kawano

Tsuyoshi Oota

Tatsuo Yoneda

Yuji Hiyama

Yoshihiro Yamaguchi

Syotaro Ono

Yusuke Kawaguchi

Akio Takano

Kiyotaka Arai

A power MOSFET includes an n-type drift layer and a p-type base layer formed in a layered manner on the n-type drift layer. Trench gates are formed to penetrate the p-type base layer to reach the n-type drift layer. On the p-type base layer, n-type source regions and p-type regions are formed. These n-type source regions and p-type regions are arranged alternately along a longitudinal direction of the trench gates. The n-type source regions and the p-type regions are arranged with a slant with respect to the longitudinal direction of the trench gates.

Semiconductor device

A first transistor has a first main electrode region which is formed so that these are subdivided into a plurality of first isolated island region. A second transistor has its first main electrode region which are divided into a plurality of second isolated island regions in close proximity to the array of first island regions.

Semiconductor device for power MOS transistor module

A semiconductor device comprising a semiconductor substrate having first and second surfaces opposing each other, the substrate including a plurality of cells sharing a common drain region, each of the cells having source and gate regions, a surface source electrode connected to the source region of each of the cells and provided on the first surface, a strap member coupled with the surface source electrode by ultrasonic waves, a gate polysilicon wiring layer connecting the gate region of each of the cells and having a silicide layer in at least a portion of a surface thereof, a surface gate electrode connected to the gate polysilicon wiring layer and provided on the first surface, and a drain electrode provided on the second surface and shared by the cells.

Silicided trench gate power mosfets ultrasonically bonded to a surface source electrode

A semiconductor device comprises a semiconductor layer of a first conductivity type (), a base region () formed proximal to the semiconductor layer, a source region () selectively placed over the base region, trenches (T), a gate insulating layer () and a gate electrode () provided on an inner wall of each of the trenches, and a source electrode () connected to the source region. The source region is higher in impurity concentration in a contact () with the source electrode than in a contact with the gate insulating layer, and it is also higher in impurity concentration in the contact () with the source electrode than in a contact with the base region.

Semiconductor device and its manufacturing method comprising a trench gate

A semiconductor device comprises a semiconductor layer of a first conductivity type ( ), a base region ( ) formed proximal to the semiconductor layer, a source region ( ) selectively placed over the base region, trenches (T), a gate insulating layer ( ) and a gate electrode ( ) provided on an inner wall of each of the trenches, and a source electrode ( ) connected to the source region. The source region is higher in impurity concentration in a contact ( ) with the source electrode than in a contact with the gate insulating layer, and it is also higher in impurity concentration in the contact ( ) with the source electrode than in a contact with the base region.

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Yokohama, Japan

Hirobumi Matsuki