Adv Antest Corporation

Hiroaki Yamoto

Rochit Rajsuman

Shigeru Sugamori

Koji Takahashi

James Alan Turnquist

Robert F Sauer

Hidenobu Matsumura

Anthony Le

Yuya Watanabe

Bruce R Parnas

Jun Makino

Kiyoshi Fukushima

A test method for testing a device under test by using an event tester is provided. The test method includes: receiving a test signal generated by the event tester and applied to the device under test and sequentially writing the same to a memory; reading sequentially the written test signal from the memory at the speed higher than that of the test signal generated by the event tester and applying the same to the device under test; acquiring the output signal outputted from the device under test in response to the applied test signal and sequentially writing the same at the speed higher than that of the test signal generated by the event tester; sequentially reading the written output signal from the memory and transmitting the same at the speed lower than that of the output signal outputted from the device under test; and determining pass/fail of the transmitted output signal by the event tester.

Test method, test system and assist board

A manufacturing process for LSIs uses an event tester simulator and an event tester to avoid prototype hold. In the LSI manufacturing method an LSI is designed under an EDA (electronic design automation) environment to produce design data of a designed LSI, and logic simulation is performed on a device model of the LSI design in the EDA environment with use of a testbench and producing a test vector file of an event format as a result of the logic simulation. Then, simulation data files are verified with use of the design data and the testbench by operating an event tester simulator, and a prototype LSI is produced through a fabrication provider by using the design data. The prototype LSI is tested by an event tester by using the test vector file and the simulation data files and test results is feedbacked to the EDA environment or the fabrication provider.

Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing

An event based test system for testing an IC device under test (DUT) designed under an automatic electronic design (EDA) environment. The event based test system includes an event memory for storing event data derived directly from simulation of design data for an intended IC in the EDA environment where the event data to denote each event is formed with time index indicating a time length from a predetermined point and an event type indicating a type of change at an event, an event generation unit for generating test vectors based on the event data where waveform of each vector is determined by the event type and a timing of the waveform is determined by accumulating the time index of previous events, and means for supplying test vectors to the DUT and evaluating response outputs of the DUT at predetermined timings.

Event based IC test system

A method for design validation of complex IC with use of a combination of electronic design automation (EDA) tools and a design test station at high speed and low cost. The EDA tools and device simulator are linked to the event based test system to execute the original design simulation vectors and testbench and make modifications in the testbench and event based test vectors until satisfactory results are obtained. The event based test vectors are test vectors in an event format in which an event is any change in a signal which is described by its timing and the event based test system is a test system for testing an IC by utilizing the event based test vectors. Because EDA tools are linked with the event based test system, these modifications are captured to generate a final testbench that provides satisfactory results.

Method for design validation of complex IC

A method of evaluating a core based SoC detects and localizes faults in the cores or interconnects between the cores with high accuracy and observability. The method includes the steps of building two or more metal layers to create core I/O pads having all I/O pads and power pads on a surface of the top metal layer of the pad frame of each core, testing the SoC as a whole by applying test vectors to the SoC through chip I/O pads and evaluating response outputs of the SoC, testing each core in the SoC by applying core specific test vectors to the core through the core I/O pads on the top metal layer of the core and evaluating response outputs of the core, and finding a location of a fault when the fault is detected when testing the SoC chip as a whole or when testing each of the cores.

Method of evaluating core based system-on-a-chip

A high speed semiconductor test system is so designed that pin cards in a test head are arranged in radial directions where the DUT is placed over the center of the test head. Since each of the pin cards is arranged radially, the side which faces the center is close to the DUT, and time critical components in the pin card are formed in an area close to the side of that faces the center, thereby minimizing the round-trip-delay (RTD).Moreover, each pin card is distanced equally from the DUT. Thus, the variation in the length of path connecting between the pin card and the DUT is minimized, and accordingly, the variation in RTD is also minimized.

High speed semiconductor test system using radially arranged pin cards

A semiconductor test system which generates a test pattern produced based on data resultant to device logic simulation performed on a computer for an LSI device designed in an electronic design automation (EDA) environment, tests the LSI device, and feedbacks the test results to the EDA environment. The semiconductor test system includes an event file for storing event data obtained by executing device logic simulation in a design stage of an LSI device under test; an event memory for storing the event data from the event file relative to timings; means for generating a test pattern by directly using the event data from the event memory and applying the test pattern to the LSI device under test; a result data file for evaluating a response output of the LSI device under test and storing resultant evaluation data; and means for evaluating design of the LSI device based on the data stored in the result data file.

Event based semiconductor test system

A method and apparatus for validating SoC (system-on-a-chip) design with high accuracy and speed and low cost. The &lsqb;apparatus allows to use a&rsqb; method &lsqb;which&rsqb; includes the steps of verifying individual cores to be integrated in an SoC by evaluating a silicon IC having a function and structure identical to that of each core constituting the SoC with use of test patterns generated based on simulation testbenches produced through a design stage of the cores; verifying interfaces between the individual cores, on-chip buses of the cores and glue logic by using the silicon ICs and simulation testbenches &lsqb;developed by an SoC designer&rsqb; and FPGA/emulation of the glue logic; verifying core-to-core timings and SoC level timing critical paths; and performing an overall design validation by using the silicon ICs and simulation testbenches of &lsqb;an&rsqb; the overall SoC &lsqb;and application runs&rsqb;.

Method and apparatus for SoC design validation

An event based test system has a modular architecture for simultaneously testing a plurality of semiconductor devices (DUT) including memory and logic devices. The test system detects functional faults as well as physical faults in the DUT. The test system includes two or more tester modules each having a plurality of pin units, a main frame for accommodating the two or more tester modules, a test fixture for electrically connecting the tester modules and the DUT, a host computer for controlling an overall operation of the test system, and a data storage for storing a library of algorithmic test patterns and software tools for producing memory test patterns for testing memories. Memory test algorithm and information regarding the design and configuration of the memories to be tested are specified prior to the memory testing.

Modular architecture for memory testing on event based test system

A semiconductor test system for testing semiconductor devices has a plurality of different tester modules and an algorithmic pattern generator (ALPG) for generating an algorithmic pattern specific to an intended memory, thereby achieving a low cost and application specific memory test system. The semiconductor test system includes two or more tester modules whose performances are different from one another, an ALPG module for generating an algorithmic pattern which is specific to the memory, a test system main frame to accommodate a combination of the tester modules and the ALPG module, a test fixture for electrically connecting the tester modules and a device under test, a performance board provided on the test fixture for mounting the device under test, and a host computer for controlling an overall operation of the test system by communicating with the tester modules through a tester bus.

Application specific event based semiconductor memory test system

An event based test system is configured to test an electronics device under test (DUT) by supplying a test signal to the DUT and evaluating an output of the DUT at a timing of a strobe signal. The event based test system includes an event memory for storing timing data of each event formed with an integer multiple of a reference clock period and a fraction of the reference clock period wherein the timing data represents a time difference between a current event and a reference point, an address sequencer for generating address data for accessing the event memory, a timing count and scaling logic for generating an event start signal, an event generation unit for generating each event based on the event start signal and data indicating the fraction of the reference clock period, and a host computer for controlling an overall operation of the event based test system.

A semiconductor integrated circuit design and evaluation system for designing an LSI device under an electric design automation (EDA) environment and for evaluating a test pattern produced based on the CAD data derived in the design stage of the LSI device. The system includes an EDA environment for designing an LSI device and evaluating functions of the designed LSI device by a device logic simulator, a dump file for storing data expressed by an event base obtained by executing the device logic simulation, an LSI tester simulator for generating a test pattern and an expected value pattern in a cycle base, a cycle-event converter for converting the test pattern from the LSI tester simulator in the cycle base to a test pattern of the event base, a first memory for storing the event based test pattern from the cycle-event converter, a second memory for storing the data from the dump file, and a comparator for synchronizing the data stored in the first and second memories by comparing the timing relationship between the two and extracting output data of the device under test from the dump file corresponding to the test pattern from the LSI tester simulator.

Semiconductor integrated circuit design and evaluation system using cycle base timing

A test circuit is capable of testing functions of a microprocessor without involving any performance penalty or substantial increase in area overhead. The test circuit includes a test control register for providing test instructions to an instruction decoder of the microprocessor, a first multiplexer for selecting either the test instructions from the test control register or instructions from an instruction fetch unit, a linear feedback shift register for providing test operand to an instruction execution unit of the microprocessor wherein the test operand is random data for executing the instruction execution unit multiple times per instruction from the test control register, a second multiplexer for selecting either the test operand from the linear feedback shift register or operand from the main memory, a multi-input feedback shift register for receiving results from the instruction execution unit, and a controller for providing the test instruction to the test control register and the linear feedback shift register and evaluating an output signature of the multi-input feedback shift register.

Circuit structure for testing microprocessors and test method thereof

A high speed evaluation apparatus for evaluating a test pattern produced for a semiconductor test system or performing a diagnostic test on a design of the semiconductor device, based on logic simulation data produced in a design stage of the semiconductor device through a CAD (computer aided design) process, without using an actual semiconductor test system or a semiconductor device. The apparatus includes an LSI tester simulator for generating a test pattern for testing a semiconductor device and an expected value pattern for comparing the output of the semiconductor device which is responsive to the test pattern, a cycle-event converter for converting the test pattern from the LSI tester simulator in a cycle base form to a test pattern of an event base form, a first memory for storing the event based test pattern from the cycle-event converter, a second memory for storing a predetermined amount of input/output data of the semiconductor device from a dump file storing data resulted from executing a logic simulation on the semiconductor device in the design stage of the semiconductor device under the CAD process, and a comparator for synchronizing the data stored in the first and second memories by comparing the timing relationship between the two and extracting output data of the device under test from the dump file corresponding to the test pattern from the LSI tester simulator.

High speed test pattern evaluation apparatus

A method of testing embedded cores in an integrated circuit chip having a microprocessor core, a memory core and other functional cores therein. The method includes the steps of; forming a plurality of registers in the integrated circuit chip, testing the microprocessor core by executing its instructions multiple times with pseudo random data and evaluating the results by comparing simulation results, applying a test program to the microprocessor core to generate a memory test pattern by the microprocessor core, applying the memory test pattern to the memory core by the microprocessor core and evaluating the response of the memory core by the microprocessor core, and testing the other functional cores by applying a function specific test pattern thereto by the microprocessor core and evaluating the resultant output signals of the functional cores.

Growing community of inventors

Santa Clara, CA, United States of America

Hiroaki Yamoto