Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Hiroaki Yabu

Katsuya Arai

Toshihiro Kogami

Shiro Usami

Toshihiro Kougami

Toshihiro Kohgami

A semiconductor integrated circuit includes: a wellof a first conductivity type formed on a substrate; a first external terminal, a second external terminal, and a third external terminalprovided above the substrate; a first protection circuitprovided on an electrical path between the first external terminaland the second external terminal; a second protection circuitprovided on an electrical path between the second external terminaland the third external terminal; and a third protection circuitprovided on an electrical path between the third external terminaland the first external terminal. A guard ringis formed continuously in the well to surround at least two circuits among the first, second, and third protection circuits, and, formed on the well

Semiconductor integrated circuit

A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality of drain contacts formed on the drain region to be spaced apart in a gate width direction of the gate electrode; and a plurality of source contacts formed on the source region to be spaced apart in the gate width direction of the gate electrode. The intervals between the drain contacts are greater than the intervals between the source contacts.

Semiconductor device

An electro static discharge protection element being formed by a diode including a well region of a first conductivity type on a surface of a semiconductor substrate, and a first diffusion layer of a second conductivity type in the well region. The first diffusion layer is surrounded by a second diffusion layer of the first conductivity type in the well region. The first diffusion layer has a surface on which a first contact region connected to an input/output terminal is formed. The first diffusion layer has a surface on which a second contact region connected to a reference voltage terminal is formed.

Semiconductor integrated circuit comprising electro static discharge protection element

A semiconductor integrated circuit includes an external pad, a ground line, a first protection circuit between the external pad and the ground line, and a second protection circuit between the external pad and the ground line. The second protection circuit is formed by a first protection element, a second protection element, and a resistor. With this structure, the resistance value of the resistor is set to an arbitrary value, so that an unnecessary current which would be generated at the time of power-off of the LSI can be decreased to a value which does not deteriorate the reliability of the LSI.

The semiconductor integrated circuit device includes: a circuit to be protected connected between a power supply line and a ground line; a first resistance connected to an external input terminal at one terminal and to an input terminal of the circuit to be protected at the other terminal; a first electrostatic discharge protection circuit including a first voltage drop circuit connected to the power supply line at one terminal and to the input terminal of the circuit to be protected at the other terminal; and a second electrostatic discharge protection circuit including a second voltage drop circuit connected to the input terminal of the circuit to be protected at one terminal and to the ground line at the other terminal.

Semiconductor integrated circuit device

An inventive semiconductor integrated circuit device includes: an external connection terminal; an electrostatic discharge protection circuit; an output circuit; an output prebuffer circuit; an input prebuffer circuit; an internal circuit; an inter-power supply electrostatic discharge protection circuit; and a substrate potential control circuit. The substrate potential control circuit includes a capacitor and a resistor. The inter-power supply electrostatic discharge protection circuit includes an NMIS transistor. When a positive surge is applied to the external connection terminal, the substrate potential of the NMIS transistor is also increased. Thus, the NMIS transistor is turned ON, and the positive electrical charge supplied to the external connection terminal is discharged toward a ground line.

An inventive semiconductor integrated circuit device includes: an external connection terminal; an electrostatic discharge protection circuit; an output circuit; an output prebuffer circuit; an input prebuffer circuit; an internal circuit; an inter-power supply electrostatic discharge protection circuit; and a gate voltage control circuit. The gate voltage control circuithas a capacitorand a resistor, and the inter-power supply electrostatic discharge protection circuithas an NMIS transistor. When a positive surge is applied to the external connection terminal, the gate potential of the NMIS transistoris also increased. Thus, the NMIS transistoris turned on, and the positive electrical charge supplied to the external connection terminalis discharged toward a ground line

A semiconductor integrated circuit of the present invention includes, between a power lineand a ground line, an NMIS transistorcapable of supplying fixed signals with low and high levels to the outside, an NMIS transistorhaving a source connected to a gate of the NMIS transistor, a PMIS transistorhaving a drain connected to a gate of the NMIS transistor, and an ESD protection power clamp circuit. If a surge is applied to the power line, the ESD protection power clamp circuitis clamped to pass the surge to the ground line. While the surge is passed, the potential of the power linerises to turn on the three transistors, and. At this time, the NMIS transistorand the PMIS transistorcan reduce the gate potential of the NMIS transistorlower than the potential of the power line

Growing community of inventors

Kyoto, Japan

Hiroaki Yabu