Fujitsu Corporation

Ricoh Company, Ltd.

Spansion Llc.

Hiroaki Watanabe

Chikahiro Deguchi

Yutaka Sekino

Shohei Yamane

Yoshiki Okumura

Yoichi Kochibe

Hideyuki Negi

Yusuke Oishi

Naoki Maezawa

Yoshihiro Kawasaki

Mitsuhiro Ono

Hideki Arakawa

Tomoyuki Ueno

Toshiyasu Ohara

Yoshinobu Higuchi

Hiroshi Fushimi

Tetsuhiko Endoh

Ryuji Tanaka

Hirotoshi Inoue

Keisuke Kanazawa

Masaki Kirinaka

Seiichi Yamaguchi

Naokazu Onda

A radiated electromagnetic wave estimation is performed by a computer. The estimation process includes: converting a circuit diagram of an electronic circuit board into a combination of a plurality of partial circuits; and predicting radiated electromagnetic waves from the electronic circuit board by using a prediction result of a radiated electromagnetic wave for each of the partial circuits obtained by the converting.

Program storage medium, method, and information processing device for radiated electromagnetic wave estimation

An estimation method is performed by a computer for estimating a far field of electromagnetic waves or heat. The method includes: generating an emphasis pattern image obtained by emphasizing each target element of a pattern image of a target circuit by an emphasizing method that corresponds to a type of each target element, with respect to the target element which is at least a part of elements included in the target circuit; and estimating the far field of electromagnetic waves or heat radiated from the target circuit by an existing estimation model using the emphasis pattern image.

Non-transitory computer-readable storage medium storing estimation program, estimation device, and estimation method

A base station capable of performing wireless communication with a wireless communication device with a Grant-free method, the base station includes: a reception circuit configured to receive a first signal transmitted from the wireless communication device by using a shared radio resource allocated to the wireless communication device; and a transmission circuit configured to transmit a second signal including information regarding a radio resource used for retransmission to the wireless communication device when retransmission of the first signal is requested to the wireless communication device.

Base station, terminal, communication method, and wireless communication system

An information processing apparatus includes an interface switching circuit including a first hardware interface to which a first device part is coupled; and a first processor including a second hardware interface, wherein the interface switching circuit is configured to block, when hot-removal of the first device part is detected, a signal path between the first hardware interface and the second hardware interface, and cancel, when diagnosis for a second device part newly hot-inserted in the first hardware interface is completed, the blocking of the signal path in response to a result of the diagnosis, and the first processor is configured to detect presence of the second device part from that the first processor transits from a non-responsive state to a responsible state, and execute an initialization process for the second device part.

Information processing apparatus and control method for suppressing obstacle

A macrocell base station includes a storage to store information of a plurality of virtual areas obtained by dividing a macrocell and information of small cells associated with the plurality of virtual areas, and a controller to perform a process of specifying the virtual area where the terminal is located, the specifying using a distance between the macrocell base station and the terminal residing in the macrocell, and a process of generating cell search information for the small cell that is to be transmitted to the terminal, the generating using the small cell information associated with the information of the specified virtual area.

Macrocell base station and terminal

A semiconductor integrated circuit includes a combinational circuit to output a state value and a parity value, a first parity check circuit to perform a parity check based on the state value and the parity value stored in a first FF circuit and output a first parity error, a second parity check circuit to perform a parity check based on the state value and the parity value stored in a second FF circuit and output a second parity error, and a selector to, when the first parity error is not output but the second parity error is output, output the state value in the first FF circuit to the combinational circuit, and when the first parity error is output but the second parity error is not output, output the state value in the second FF circuit to the combinational circuit.

Semiconductor integrated circuit and method of processing in semiconductor integrated circuit

A data receiving circuit includes a generating unit that generates multiple clocks with different phases from one another. The data receiving circuit includes multiple acquiring units that acquire data from a received data signal by using different clocks from one another out of the multiple clocks generated by the generating unit. The data receiving circuit includes a determining unit that determines whether the data acquired by the multiple acquiring units are consistent. The data receiving circuit includes a correcting unit that corrects the phases of the multiple clocks in a direction in which data inconsistency does not occur when the determining unit has determined that there is data inconsistent with the other data in the data acquired by the multiple acquiring units.

Data receiving circuit, information processing apparatus, a computer readable storage medium, and data receiving method

For example, in a radio communication system using an OFDMA method, frequency bandwidth allocated to each sector is modified according to, for example, the number of terminals existing in each sector, and the effective utilization of radio sources is promoted. A radio base station device includes unit to determine the amount allocated to each sector from the amount of radio resources in the base station and unit to switch over the connection states of a plurality of radio resources obtained by dividing the entire radio resources that can be allocated to each sector in the base station according to the determined amount of allocation.

Radio base station device and radio resource connection switching method

A configuration method performs a configuration of a FPGA circuit by setting configuration data from a configuration circuit to the FPGA circuit. The method counts, within the FPGA circuit, a number of times a configuration of the FPGA circuit fails. The method adjusts, within the FPGA circuit, the configuration data at a time when the configuration failed if the counted number exceeds an upper limit value, and re-executes the configuration based on the adjusted configuration data. The method sets the configuration data in which the configuration is succeeded from the FPGA circuit to the configuration circuit when the configuration is successful.

Configuration method and FPGA circuit re-executing configuration based on adjusted configuration data

A N-level cell memory controlled by the memory controller of the invention have an internal configuration in which the plurality of data input/output terminals connected to the second data bus are separated into first through Mth data input/output terminal groups, such that there is no redundancy in the n bits of data associated with one N-level cell. Together with this, the memory controller separates the plurality of data bits on the first data bus into first through Mth data groups, the ECC circuits generate error-correction codes for each of these data groups, and the first through Mth data groups and first through Mth error correction codes are input to the first through Mth data input/output terminals of the N-level cell memory, via the second data bus.

Memory controller for multilevel cell memory

An interface between a card-type peripheral device and a host machine, such as a PC, determines the operational supply voltage required to operate the peripheral device prior to the host machine supplying the operational supply voltage to the peripheral device. The host machine first receives information stored on the peripheral device specifying the operational voltage required to operate the peripheral device. The host machine then generates the proper operational supply voltage and provides it to the peripheral device. The interface prevents damage to the peripheral device due to the host machine supplying an incorrect operational voltage.

Host machine interface for reading information stored in peripheral card

A bus to which a bus control circuit and at least one electronic circuit are connected is controlled by a) storing a signal level which is output to the bus when the bus is in an active state, and b) fixing the bus to the signal level stored in the step a) when the bus switches to an inactive state.

Method and circuit for controlling a bus in system and semiconductor

An automatic frequency controller synchronizes a received carrier signal with a simulated carrier signal to automatically control a center frequency of the simulated carrier signal. The received carrier signal has a first synchronous code pattern inserted into a plurality of frame periods and a second synchronous code pattern inserted into a plurality of multiframe periods. The phase of the received carrier signal is determined by sweeping the center frequency of the simulated carrier signal and mixing the simulated carrier signal with the received carrier signal. The sweep of the center frequency of the simulated carrier signal is reduced when frame synchronization is detected and the sweep of the center frequency is fixed when multiframe synchronization is detected.

Growing community of inventors

Kawasaki, Japan

Hiroaki Watanabe