Taiyo Yuden Co., Ltd.

Hiroaki Toguchi

Masayuki Sato

Takashi Ishiguro

Tetsuo Hironaka

Naoki Hirakawa

Kazuya Tanigawa

FPGAs and MPLDs, which are conventional programmable semiconductor devices, have had poor cost performance and did not suitably take long signal lines into account. To solve this, a flip-flop is built into each MLUT block comprised of a plurality of MLUTs, each MLUT comprising a memory and an address-data pair. With respect to the adjacent line between adjacent MLUTs, alternated adjacent line are introduced, while in the case of interconnects between non-adjacent MLUTs, dedicated distant line and, furthermore, a torus interconnect network are provided.

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Okazaki, Japan

Hiroaki Toguchi