Other

Renesas Technology Corp.

Mitsubishi Electric Engineering Company, Limited

Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Fuji Jukogyo Kabushiki Kaisha

Hiroaki Tanizaki

Tsukasa Ooishi

Hideto Hidaka

Takaharu Tsuji

Masatoshi Ishikawa

Shigeki Tomishima

Hiroshi Kato

Mitsutaka Niiro

Yasumitsu Murai

Masanao Maruta

Hiroki Shimano

Shuichi Ueno

Nobuo Ando

Tomoshi Futatsuya

Yuichi Kunori

Yutaka Komai

Masanori Hayashikoshi

Yukinori Hatou

Mitsue Takahashi

Kenji Koda

A semiconductor device having first and second digit line drivers and a bit line driver. When the address of one segment has been input from the outside, a segment decoder selects one segment corresponding to the address and couples the same to the selected first digit line driver. When the addresses of two or more segments have been input from the outside, the segment decoder selects two or more segments corresponding to the addresses and couples the selected two or more segments to the respective digital line drivers.

Semiconductor device

The present invention provides a semiconductor device having a nonvolatile memory function capable of shortening an erase time and executing data access efficiently. When, under the control of a command register/control circuit, an erase voltage is applied to an embedded erase gate wiring disposed in a memory cell boundary region, and an electrical charge is transferred between a floating gate and an embedded erase gate to thereby perform an erase operation, a read selection voltage is applied to a memory gate line and an assist gate line during the application of the erase voltage to thereby carry out the reading of data.

A magnetic memory device is provided in which, even when a recording layer having an asymmetric shape and a local via are formed over a strap wiring with a sufficient distance allowed therebetween, increase in the size of the magnetic memory device can be suppressed. The magnetic memory device includes the strap wiring, the local via, and a magnetic recording element (TMR element). The TMR element includes a fixed layer and the recording layer. The planar shape of the recording layer is asymmetric with respect to the direction of the easy magnetization axis of the recording layer and is symmetric with respect to the axis of symmetry perpendicular to the easy magnetization axis. The contoured portion of the recording layer on the side closer to the center of area of the recording layer is opposed to the local via formation side.

Magnetic memory device

The invention provides a negative electrode material for use with a lithium-ion capacitor, which is high in energy density, output density and excellent in durability. When graphite of which an average distance between 002 lattice planes thereof is within a range from 0.335 nm to 0.337 nm is used for an active material of a negative electrode of a lithium-ion capacitor, the energy density of the capacitor is increased. The output characteristic and the cycle durability can be improved when D, Dand Dare set within predetermined ranges.

Lithium-ion capacitor

Source lines for a spin injection magnetic memory cell are arranged parallel to word lines for executing writing/reading of data multiple bits at a time. In a write operation, a source line potential changes in a predetermined sequence such that the source line commonly connected to a plurality of selected memory cells is set to pass a current only in one direction in each stage of the operation sequence. For the data write sequence, a current is caused to flow through memory cells according to write data sequentially, or the memory cell has a resistance state set to an initial resistance state before writing, and then changed to a state according to the write data Fast writing can be achieved in the magnetic memory without increasing a memory cell layout area.

Nonvolatile semiconductor memory device

A path routing from a write current source supplying a write current through an internal data line, a bit line and a source line to a reference potential except a memory cell is configured to have a constant resistance independent of a memory cell position selected in a memory array, and each of the resistance value of the current path between the memory cell and the write current source and the resistance value of the current path between the selected memory cell and the reference potential node is set to 500&#x3a9; or lower. A nonvolatile semiconductor memory device having improved reliability of data read/write is achieved.

A tunneling magneto-resistance element is arranged on an upper layer side of a digit line. The tunneling magneto-resistance element is electrically coupled to a source/drain region of an access transistor through a strap and a contact hole. A bit line is electrically coupled to the tunneling magneto-resistance element, and arranged on the upper layer side of the tunneling magneto-resistance element. A plurality of tunneling magneto-resistance elements share one access transistor, so that a non-volatile memory device achieving low area penalty and higher integration can be implemented.

Non-volatile memory device having toggle cell

During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.

Thin film magnetic memory device reducing a charging time of a data line in a data read operation

Normal memory cells and dummy cells are arranged continuously in a memory array. In a data read operation, first and second data lines are connected to the selected memory cell and the dummy cell, respectively, and are supplied with operation currents of a differential amplifier. An offset corresponding to a voltage difference between first and second offset control voltages applied from voltage generating circuits are provided between passing currents of the first and second data lines, and a reference current passing through the dummy cell is set to a level intermediate between two kinds of levels corresponding to storage data of a data read current passing through the selected memory cell.

Thin film magnetic memory device provided with a dummy cell for data read reference

A programming circuit includes an LT fuse read circuit programming a defective address during a wafer-processing, an electrical fuse circuit electrically programming a defective address, an electrical fuse circuit storing therein whether the electrical fuse circuit is used, a select circuit receiving data programmed by the LT fuse and that programmed by the electrical fuse for switch and output, an electrical fuse circuit designating a switching of the select circuit, and a repair decision circuit comparing an output received from the select circuit and an input address received from the address buffer.

Semiconductor integrated circuit device and semiconductor memory device reprogrammable after assembly

A write-driver/read-amplifier circuit includes a write driver, a GIO equalize circuit and a read amplifier. When a current leaks from or to global data line, a signal applied to a logic gate attains L-level. As a result, the write driver and the GIO equalize circuit stop the operations so that a semiconductor memory device can prevent occurrence of an unnecessary leak current.

Semiconductor memory device having a plurality of signal lines for writing and reading data

An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.

Semiconductor integrated circuit device with internal power supply potential generation circuit

A dummy cell has a plurality of dummy magneto-resistance elements which have the same characteristic as a magneto-resistance element, which characteristic changes corresponding to a voltage applied to the opposite ends. In addition, a voltage applied to opposite ends of each dummy magneto-resistance element is made smaller than a voltage applied to opposite ends of a magneto-resistance element of a memory cell. With this, the dummy cell is designed so as to have an intermediate electric resistance between first and second electric resistances.

Thin film magnetic memory device having dummy cell

In one data read operation, data read for reading stored data before and after a predetermined data write magnetic field is applied to a selected memory cell, respectively, is executed, and the data read is executed in accordance with comparison of voltage levels corresponding to the data read operations before and after application of the predetermined data write magnetic field. In addition, data read operations before and after the application of a data write magnetic field are executed using read modify write. It is thereby possible to avoid an influence of an offset or the like resulting from manufacturing irregularities in respective circuits forming a data read path, to improve efficiency of the data read operation with accuracy and to execute a high rate data read operation.

Thin film magnetic memory device executing self-reference type data read

A plurality of bit lines are divided into a plurality of groups each including Y (Y: integer of at least two) bit lines. Y data read data lines passing a data read current therethrough in data reading are provided along with Y connection control parts electrically coupling Y bit lines and the Y read data lines with each other every group. Therefore, the connection control parts electrically connected with the Y read data lines are uniformly divided so that parasitic capacitance applied to the read data lines following electrical connection with the connection control parts can be suppressed. Therefore, the time for charging the read data lines to a prescribed voltage level can be reduced for executing high-speed data reading.

Growing community of inventors

Hyogo, Japan

Hiroaki Tanizaki