Seiko Instruments Inc

Agency of Industrial Science and Technology

Ablic Inc.

Other

Ns Solutions Corporation

Agency Industrial Science

Hiroaki Takasu

Yoshikazu Kojima

Kunihiro Takahashi

Tsuneo Yamazaki

Masaaki Kamiya

Yutaka Hayashi

Hitoshi Niwa

Nobuyoshi Matsuyama

Jun Osanai

Tadao Iwaki

Tomoyuki Yoshino

Sukehiro Yamamoto

Atsushi Sakurai

Hiroshi Suzuki

Hisashi Hasegawa

Kenichi Kondo

Masaaki Taguchi

Satoru Yabe

Ryuichi Takano

Atsushi Iwasaki

Kazuhiro Yamada

Kenji Kitamura

Hideaki Tanaka

Kunio Nakajima

Mizuaki Suzuki

Takayuki Takashina

Hitomi Watanabe

Yoshio Hattori

Naoto Inoue

Mika Shiiki

Hiroya Suzuki

Takashi Mitsubuchi

Kazunari Sugiura

Noritoshi Ando

Yasuhiro Mitsuno

Yomoyuki Yoshino

Isao Sonobe

Sumitaka Goto

Yoko Serizawa

Michiaki Yazawaw

A semiconductor device has an off transistor () in which a gate electrode () and a source region () of an N-type MOS transistor are connected to a ground terminal and a drain region () is connected to an external signal terminal (). In the off transistor (), the gate electrode () is extensively provided over a portion or entirety of the drain region () in addition to a channel region. A capacitance (C) formed between the gate electrode () and the drain region () may be greater than a capacitance (C) generated between the gate electrode () and a ground potential.

Semiconductor device

Provided is a semiconductor device that allows reduction of a measurement time of a PCMTEG and improvement of productivity in an IC manufacturing process. A PCMTEG regionformed on a surface of a semiconductor substrate is divided into a main PCMTEG regionand a sub-PCMTEG region, and TEGs having specifications for their electrical characteristic values are all collectively arranged in the sub-PCMTEG region

Semiconductor device and method of testing a semiconductor device

A plurality of feature values are extracted from input data as document data, distributed representations of words that correspond to the respective extracted plurality of feature values is obtained, and the extracted plurality of feature values are aggregated into a plurality of classifications based on the obtained distributed representation.

Information processing apparatus, information processing method, and program

A thin film resistor includes a high-resistance region and low-resistance regions which are formed at both ends of the high-resistance region. The high-resistance region includes first high-resistance regions and a second high-resistance region, and the first high-resistance regions are arranged at both side surfaces in a first direction in the second high-resistance region. The second high-resistance region has a higher sheet resistance than that of the first high-resistance regions.

Semiconductor device and method of manufacturing the same

Provided is a semiconductor device capable of improving relative accuracy of semiconductor elements and a yield of a semiconductor integrated circuit device. The semiconductor device includes a flat region formed on a surface of a semiconductor substrate, and having an outer peripheral shape formed by regional sides and regional chamfer portions; an outer peripheral region surrounding the flat region, and having a uniform height different from a height of the flat region; a plurality of semiconductor elements having similar shapes or the same shape, and formed on the flat region; and a wiring metal connecting the plurality of semiconductor elements via contact holes formed in a second insulating film on the semiconductor elements.

Semiconductor device having a flat region with an outer peripheral shape including chamfer portions

In order to suppress an off leak current of an off transistor for ESD protection, in an NMOS for ESD protection whose isolation region has a shallow trench structure, a drain region is placed apart from the shallow trench isolation region so as not to be in direct contact with the shallow trench isolation region in a region where the drain region of the NMOS transistor for ESD protection is adjacent to at least a gate electrode of the NMOS transistor for ESD protection.

Provided is an electrically erasable and programmable nonvolatile semiconductor memory device whose tunnel region formed in the drain region has the second conductivity-type low-impurity-concentration region with the first tunnel insulating film for solely injecting electrons disposed thereon, and the first conductivity-type low-impurity-concentration region with the second tunnel insulating film for solely ejecting electrons disposed thereon, both regions fixed to the same potential as the drain region and having a lower impurity concentration than that of the drain region.

Nonvolatile semiconductor memory device

Provided is an electrically erasable and programmable nonvolatile semiconductor memory device having a tunnel region; the tunnel region and the peripheral of the tunnel region are dug down to be made lower, and a depletion electrode, to which an arbitral potential is given to deplete a part of the tunnel region through a depletion electrode insulating film, is arranged in the lowered drain region.

Provided is an electrically erasable and programmable nonvolatile semiconductor memory device having a small hole in a second conductivity-type drain region, a tunnel insulating film formed on the surface of the hole, and a protrusion extended from the floating gate electrode and arranged to fill the hole. Further a tunneling restriction region which is an electrically floating first conductivity type region arranged in a vicinity of the surface of the drain region around the hole to define the size of the tunnel region through which the tunnel current flows.

In a manufacturing method for an image sensor integrated circuit, a plurality of pixel regions each having a photodiode are arranged on a silicon substrate. A light-transmissive conductive film is formed over the silicon substrate. A protective film is formed on the light-transmissive conductive film while holding a potential of the light-transmissive conductive film at the same potential as that of the silicon substrate.

Manufacturing method for image sensor IC

A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. The third region and the second region are in contact with each other and make a low resistance junction. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode. One of the first and the fourth regions is used as an output region according to a circuit operation.

Field effect transistor formed on an insulating substrate and integrated circuit thereof

A semiconductor device for performing photoelectric conversion of incident light includes a substrate and a well region having different conductivity types. A depletion layer is generated in a vicinity of a junction interface between the substrate and the well region. A first trench has a depth equal to a height up to a top portion of the depletion layer generated on a bottom side of the well region and a width extending to a heavily doped region formed in the well region. A second trench has a depth larger than that of a portion of the depletion layer generated on the bottom side of the well region and a width larger than that of portions of the depletion layer generated on the sides of the well region. The second trench surrounds the first trench so as to confine the depletion layer under the first trench except for a region thereof under the heavily doped region. An insulator is buried into each the first trench and the second trench.

Semiconductor device for performing photoelectric conversion

In a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection surrounded by a shallow trench for device isolation, in order to suppress the off-leak current in an off state, there is formed, in the vicinity of the drain region of the NMOS transistor for ESD protection, an n-type region receiving a signal from an external connection terminal via a p-type region in contact with the drain region of the NMOS transistor for ESD protection.

A semiconductor device has an external connection terminal, an internal circuit region, an ESD protection N-MOS transistor provided between the external connection terminal and the internal circuit region to protect an internal element formed in the internal circuit region, and a shallow trench structure provided to isolate the ESD protection N-MOS transistor. A thin insulating film is formed on a drain region of the ESD protection N-MOS transistor. An electrode is disposed above the drain region and on the thin insulating film for receiving a signal from the external connection terminal. The thin insulating film has a film thickness and film properties that allow dielectric breakdown and establish conduction between the electrode and the drain region when a voltage exceeding an absolute maximum rating of the semiconductor device is applied to the electrode.

Provided is a semiconductor device in which the first trench isolation regions is placed between a substrate potential-fixing P-type diffusion region of an ESD protection NMOS transistor and source and drain regions of the ESD protection NMOS transistor, and has a depth greater than a depth of the second trench isolation region that is placed between a substrate potential-fixing P-type diffusion region of an NMOS transistor for internal circuit and source and drain regions of the NMOS transistor for internal circuit.

Growing community of inventors

Chiba, Japan

Hiroaki Takasu