Fujitsu Corporation

Hiroaki Shiraishi

Kouichi Tanda

Yoshikatsu Kouhara

Takakazu Tokunaga

Koji Takatomi

Masaru Nishida

Yoshinori Soejima

Katsuhiko Hirashima

Kazuyuki Inomoto

Naoyuki Takeshita

Junichi Sawada

Shinji Takao

Yoshinobu Takagi

Ichiro Kagami

Tateo Shimaru

Masao Mutou

Hisaya Urabe

Mineo Kotegawa

Tsuneharu Suzuki

Yushi Nobayashi

A transmission apparatus includes a first storage configured to store data received from external into a write enable area, a second storage configured to store the data in accordance with a write request and output a retry request in response to occurring an error of writing a first data included in the data, and a controller configured to read the data from the first storage and send the write request to the second storage, set an area of the first storage storing the first data to a write disable area in combination with stop sending the retry request to external when receiving the retry request from the second storage, and send the first data reading from the write disable area of the first storage to external in response to a read request from external.

Transmission apparatus and retry method

A computer terminal retrieves pin data related to respective pins of a plurality of Field Programmable Gate Array that are mounted on a board. The computer terminal retrieves setting data related to a connection check. Upon retrieving the pin data and the setting data, the computer terminal assigns, as data for the connection check to all the pins that can output data, unique data that is unique to each pin. The computer terminal generates input pin data and output pin data containing the unique data, stores therein the input pin data and the output pin data, and generates checking circuits that check connections between output pins and input pins. The computer terminal generates checking data based on the checking circuits.

Data generating method, connection checking system, and computer product

A method and apparatus for generating file information including setting clock information regarding a clock condition and a clock speed to be used by a speed conversion circuit block, reconstructing the clock circuit block including a new clock for accommodating insertion of the speed conversion circuit block, and associating connection terminal information indicating a connection relationship of connection terminals with speed conversion object information having set, as a speed conversion object, a connection terminal requiring connection speed conversion. The connection terminal information of the connection terminal set as the speed conversion object is extracted, speed conversion circuit information indicating a connection relationship of the connection terminals in the speed conversion circuit block and connection terminal information having the connection relationship of the connection terminals reconstructed is generated, and file information in which the speed conversion circuit block is inserted between the clock circuit block and the interface block is generated.

File information generating method, file information generating apparatus, and storage medium storing file information generation program

A computer is allowed to execute an information acquisition process that acquires a file expressing information on pins used in respective ports provided in each block of a logic circuit to be redesigned and information indicating connection relationships between the ports (#); execute a multiplexer disposition process that, based on the file, classifies pins of output ports of a block into a number of pin groups that is less than the number of pins, and disposes a multiplexer having a function to multiplex a signal output from each pin classified in the same pin group (#); and execute a demultiplexer disposition process that, based on that file, disposes a demultiplexer having a function to demultiplex signals that have been output from output ports of a block and multiplexed by the multiplexer, and a function to output each demultiplexed signal to input ports of respective input destination blocks (#).

Logic circuit redesign program, logic circuit redesign apparatus, and logic circuit redesign method

A method is disclosed for setting a master node of a ring network that has adjacently connected nodes situated on rightward and leftward lines of a bidirectional transmission channel. The method includes the steps of: counting the number of nodes interposed between a designated node and each node other than the designated node on the rightward and leftward lines of the bidirectional transmission channel; and setting one of the nodes as the master node. The master node satisfies a relation of, NHC_L=NHC_R or NHC_L=NHC_R-, wherein NHC_L is the number of interposed nodes counted from the leftward line, and NHC_R is the number of interposed nodes counted from the rightward line.

Method and apparatus for setting master node of ring network

Growing community of inventors

Fukuoka, Japan

Hiroaki Shiraishi