Renesas Electronics Corporation

Mitsubishi Denki Kabushiki Kaisha

Hiroaki Sekikawa

Masatoshi Kimura

Kaoru Motonami

Hidenori Sato

Takahiro Mori

Hideki Sasaki

Masaaki Shinohara

Takeshi Iwamoto

Atsushi Amo

Takuya Maruyama

Kakutaro Suda

Yotaro Goto

Yoshitaka Fujiishi

Shigeo Tokumitsu

Yasuhiro Ido

Hideki Doi

Yuji Ishii

Rui Toyota

Kazuhide Kawabe

Hiroyasu Nousou

Asuka Komuro

Hajime Hayashimoto

Reliability of a semiconductor device is improved. The semiconductor device includes a clip which is electrically connected to a main-transistor source pad via a first silver paste and is connected to a lead via a second silver paste. The clip has a 'first part' with which the first silver paste is in contact, a “second part” with which the second silver paste is in contact, and a “third part” positioned between the “first part” and the “second part”. A protruding member is formed on a surface of the main-transistor source pad, and the “first part” is in contact with the protruding member.

Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device of one embodiment includes the steps of: forming a drift region in a first surface of a semiconductor substrate; forming a body region having a first portion disposed in the first surface, and a second portion disposed in the first surface so as to surround the first portion and the drift region; forming a hard mask, having an opening over the drift region, in the first surface; forming a reverse conductivity region in the first surface by ion implantation using the hard mask; forming a trench in the first surface by anisotropic etching using the hard mask; and embedding an isolation film in the trench. The ion implantation is performed obliquely to the first surface such that ions are implanted below a first edge part, which is located on a first portion side of the opening, of the hard mask.

Semiconductor device and method of manufacturing semiconductor device

A substrate contact plug which is connected to a wiring and a semiconductor substrate and does not form a circuit is formed in a seal ring region in a peripheral portion of a semiconductor chip region. The substrate contact plug is buried in a trench which is deeper than an element isolation trench.

Semiconductor device including a substrate contact plug and manufacturing method thereof

When a trench that penetrates a semiconductor substrate in a scribe region in a solid-state imaging element of a back side illumination type, occurrence of contamination of the solid-state imaging element caused by an etching step for foaming the trench or a dicing step for singulating a semiconductor chip is prevented. When a silicide layer that covers a surface and the like of an electrode of a transistor is formed, in order to prevent formation of the silicide layer that covers a main surface of the semiconductor substrate in the scribe region, the main surface of the semiconductor substrate is covered with an insulation film before a forming step for the silicide layer.

Semiconductor device and method for manufacturing same

A semiconductor device includes a plurality of wirings (WR) which are formed in the same layer above a semiconductor substrate, and a plurality of wirings (WR) which are formed in the same layer as that of the plurality of wirings (WR). The plurality of wirings (WR) are extended in an X axis direction and arranged at a pitch (PT) in a Y axis direction intersecting with the X axis direction when seen in a plan view, and the plurality of wirings (WR) are extended in the X axis direction and arranged at a pitch (PT) in the Y axis direction when seen in a plan view. The plurality of wirings (WR) are electrically connected to the plurality of wirings (WR), and the pitch (PT) is smaller than the pitch (PT).

Semiconductor device and manufacturing method of the same

To provide a semiconductor device having improved reliability. The semiconductor device is equipped with a first polyimide film, rewirings formed over the first polyimide film, first and second dummy patterns formed over the first polyimide film, a second polyimide film that covers the rewirings and the dummy patterns, and an opening portion that exposes a portion of the rewirings in the second polyimide film. The first dummy pattern is, in plan view, comprised of a closed pattern surrounding the rewirings while having a space therebetween.

Semiconductor device and method of manufacturing same

A connection portion connects a copper-based first wiring layer with a copper-based second wiring layer arranged on the upper side of a first diffusion barrier film. The first diffusion barrier film includes a first opening region formed in a semiconductor circuit region that is a partial region in a two-dimensional view and a second opening region formed as an opening region different from the first opening region in a two-dimensional view. The opening regions are formed in a region different from an opening region formed to allow the connection portion to pass through the first diffusion barrier film. A mark wiring layer is arranged immediately above the second opening region as the same layer as the second wiring layer. A second diffusion barrier film is arranged in contact with the upper surface of the mark wiring layer.

A semiconductor storage device is provided, which inhibits shorts between cells to improve operational reliability and contributes to high-speed operation. An active region () where DRAM cells are formed is defined by an isolation trench () formed in a silicon substrate (). The isolation trench () has an isolation insulating film () formed therein. Each DRAM cell includes a MOS transistor having a gate electrode () with sidewalls (), and a capacitor having an upper electrode () with sidewalls (). A recess () is formed in the upper portion of the isolation trench (), and the upper electrode () of the capacitor has a buried portion buried in the recess (). The outer edge (E) of the buried portion of the upper electrode () is located inside the outer edge (E) of the sidewalls ().

Semiconductor storage device

A semiconductor device includes: an insulation layer; a fuse layer extending on the insulation layer in one direction and disconnected through light radiation to control a redundant circuit; a pseudo fuse layer on the insulation layer along at least one side of the fuse layer; another insulation layer covering the fuse layer and the pseudo fuse layer; and a protection film formed on another insulation layer and having an opening in a region opposite to the fuse layer. Fuse layers having a spacing of less than 4 &mgr;m or 4.5 to 5.5 &mgr;m. Such a structure allows a semiconductor device with a fuse layer capable of being disconnected reliably and providing a smaller blow trace.

Semiconductor device having a fuse layer

In a semiconductor device having a DRAM memo cell and a peripheral circuit, source/drain regions of transistors composing the memory cell are not silicided to restrict a junction leak and to improve a refresh characteristic; surfaces of source/drain regions and gate electrodes of transistors composing the peripheral circuit are silicided to reduce resistance of contacts and resistance of wirings for enabling a high-speed operation; side walls made of insulating material are formed on sides of the gate electrodes of the transistor composing the peripheral circuit to serve as a mask when impurities are injected for forming the source/drain regions; and insulating material laminated in the memory cell serves as a mask against siliciding.

Growing community of inventors

Tokyo, Japan

Hiroaki Sekikawa