Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Hiroaki Segawa

Masanori Hirofuji

Tooru Matsui

Tatsuya Naruse

Shusaku Ota

Yoshifumi Kumashiro

An electrode pad is provided above a circuit block of a semiconductor integrated circuit device. A junction point A and a junction point B are provided on connection lines connecting electrode pads to an internal circuit and an electrostatic discharge (ESD) protection circuit. The junction point A and the junction point B are positioned at locations closer to the ESD protection circuit than to the electrode pads.

Semiconductor integrated circuit device

Plural I/O cells () having electrode pads for wire bonding () are disposed with spaces () between them in the vicinity of a corner of an I/O region () of a semiconductor substrate (), and power supply separation cells () not to be wire bonded, on which ESD (electrostatic discharge) protection circuits () having ESD protection transistors are amounted, are disposed between the respective I/O cells (), whereby the chip size is reduced upon consideration of layout of the electrode pads.

Semiconductor device

A power supply potential and a ground potential are supplied to a test-use power supply pad and a test-use ground pad, respectively. The power supply potential supplied to the test-use power supply pad is transferred to power supply lines and then to each circuit block via a test-use power supply line and a potential transfer circuit including a diode device. A voltage drop is caused by each of the diode devices. To cope with the voltage drop, however, respective sizes of the diode devices and resistance components of the potential transfer circuits are configured so that a uniform voltage drop is generated at each of the power supply lines.

Growing community of inventors

Osaka, Japan

Hiroaki Segawa