Sony Corporation

Mitsubishi Electric Corporation

Mitsui Chemicals, Inc.

Sony Semiconductor Solutions Corporation

Hiroaki Sakaguchi

Koichi Hasegawa

Masaaki Ishii

Hiroshi Yoshikawa

Taichi Hirao

Hiroshi Kobayashi

Takashi Abe

Mitsuru Kitazaki

Hitoshi Kai

Masaki Sugawara

Masaaki Kawasaki

Akihiro Takahashi

Takeshi Ito

Haruhisa Yamamoto

Yoshiharu Kikuchi

Takashi Hakuta

Mitsunao Arino

Kaoru Ueno

Kazuto Usaka

Tomoki Okuno

Mitsuko Nagai

Hisashi Kawanabe

Katsuhiko Metsugi

Yousuke Morita

Masao Kishi

Michio Sekine

Hideki Todoroki

Hisashi Hokonohara

Tetsushi Masuno

An apparatus base model is a model for defining apparatuses in an air conditioner management system from apparatus data that includes information regarding each item managed for the apparatuses. An SW generation unit is configured so as to associate the apparatus data with the apparatus base model on the basis of the apparatus data and thereby generate apparatus control SW for managing the apparatuses in the air conditioner management system.

Apparatus management device and software generation method

Ranging devices are disclosed. In one example, a ranging device includes a control register that holds a pixel mode. A pixel array includes light receiving units each detecting the incidence of photons. A reading circuit reads detection signals from each light receiving element with a sampling period. A pixel value generating circuit tallies, in units of pixels, the number of detection signals read from each light receiving element, and generates, for each sampling period, the pixel value of each pixel. A memory stores, for each pixel, a histogram of the pixel values in each sampling period. In a first pixel mode, an area having a first size in the memory is allotted to each pixel. In a second pixel mode, an area having a different, second size in the memory is allotted to each pixel.

Ranging device and ranging method

Parallel processing suitable for convolution operation in a convolutional neural network is executed. Each of a plurality of selectors sequentially selects data, which is held in a two-dimensional shift register, in predetermined two-dimensional regions at least partially different from each other. Each of a plurality of two-dimensional convolution operation circuits multiplies the data selected by the corresponding selector by coefficient data stored in a coefficient memory and accumulates results of the multiplication to calculate, in parallel, two-dimensional convolution operation results in the two-dimensional regions. Each of a plurality of adder circuits adds operation results of the two-dimensional convolution operation circuits in a channel direction to output a three-dimensional convolution operation result.

Operation processing circuit and recognition system

To prevent a bank conflict in a memory with respect to an access address interval of a wide range. In a plurality of memory modules, an address is provided in a circulation manner for each word. A plurality of access ports is input/output ports for accessing the plurality of memory modules. A plurality of address converting sections converts the address to rearrange an arrangement of the words in the plurality of memory modules by a transposing process for a square matrix of a predetermined size. A connecting section connects the plurality of memory modules and the plurality of access ports in accordance with a result of the address conversion.

Memory control apparatus, memory apparatus, information processing system, and memory control method

An air conditioning device remote control apparatus is provided with a transmission unit that transmits an operation signal to an associated air conditioning device, a wireless communication unit that performs wireless communication with an external wireless communication device or another remote control apparatus, and a main control unit that controls the transmission unit and the wireless communication unit. In a case in which the wireless communication unit receives an operation signal from the external wireless communication device or the another remote control apparatus, the main control unit transmits the operation signal to the associated air conditioning device, and performs detection of another remote control apparatus emitting radio waves. In a case in which the wireless communication unit detects another remote control apparatus emitting radio waves, the main control unit transmits, via the wireless communication unit, the operation signal to the another remote control apparatus emitting radio waves.

Air conditioning device remote control apparatus and air conditioning system

The present technology relates to an arithmetic processing device and an arithmetic processing method that enable the reduction of a circuit area while lowering power consumption, in performing more reliable arithmetic operations of a neural network. In arithmetic operations of the neural network, the arithmetic processing device makes a specific part of bits of a weighting coefficient and input data used for the arithmetic operations redundant such that redundancy of the specific part of bits becomes larger than redundancy of remaining bits except the specific part of bits, thereby being able to reduce the circuit area while lowering the power consumption in performing reliable arithmetic operations of the neural network. The present technology can be applied to, for example, an arithmetic processing device configured to perform arithmetic operations of a neural network.

Arithmetic processing device and arithmetic processing method

Provided is a management apparatus, which is to be connected to a device, and is configured to manage the device. The management apparatus includes: a display unit configured to display a state of the device; and a wireless communication unit configured to wirelessly communicate to and from a mobile terminal. When a distance between the mobile terminal and the management apparatus has become smaller than a threshold value, the management apparatus displays on the display unit management program information on a management program for managing the device.

Management apparatus and air-conditioning system

Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage sectionof a cache memory holds a reference number fieldin addition to a tag address field, a valid field, and a dirty field. The reference number fieldis set in a data write, and the value thereof is decremented after each read access. When the value of the reference number fieldis changed from '1' to '0', the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.

Data transfer in a multiprocessor using a shared cache memory

A remaining memory capacity of a memory is acquired in a predetermined cycle, and remaining memory capacity MR is stored in a remaining capacity database in association with an acquisition date. After that, it is determined whether or not a memory leak is present based on the remaining memory capacity and the acquisition date stored in the remaining capacity database. When it is determined that the memory leak possibly occurs, a usage limit period being a length of time to a point when a forced restart according to a usage limit threshold is performed is computed based on the remaining memory capacity and a memory decreasing rate. A restart schedule (and an all-stop period) is set within the usage limit period. On a date of the restart schedule, a management apparatus for managing an air-conditioning apparatus is restarted.

Management apparatus and method of managing air-conditioning apparatus

Cache memory and cache memory control unit

Certain aspects of an apparatus and method for interconnection may include an interconnection section, a request processing section and a response processing section. The interconnection section may be configured to transfer a request from a master interface bus to a slave interface bus and to transfer a response from the slave interface bus to the master interface bus. A slot number within the request specifies a time slot during which the interconnection section may be permitted to transfer the response to the master interface bus. The request commands the processing section to load the slot number into a management table. The response commands the response processing section to read out the slot number from the management table.

Interconnection apparatus and controlling method therefor

An instruction fetch apparatus is disclosed which includes: a program counter configured to manage the address of an instruction targeted to be executed in a program in which instructions belonging to a plurality of instruction sequences are placed sequentially; a change designation register configured to designate a change of an increment value on the program counter; an increment value register configured to hold the changed increment value; and an addition control section configured such that if the change designation register designates the change of the increment value on the program counter, then the addition control section increments the program counter based on the changed increment value held in the increment value register, the addition control section further incrementing the program counter by an instruction word length if the change designation register does not designate any change of the increment value on the program counter.

Instruction fetch apparatus, processor and program counter addition control method

Disclosed herein is an arithmetic decoding apparatus including an instruction decoder configured to decode an arithmetically encoded data decoding instruction to be executed for carrying out an arithmetic-decoding process of arithmetically decoding arithmetically encoded data into a binary signal; an execution condition code holding section configured to hold the binary signal obtained as a result of an immediately preceding arithmetic-decoding process as an execution condition code; and an arithmetic decoding execution section configured to determine whether a context number specified by the arithmetically encoded data decoding instruction is to be used as a context index as it is or the specified context number incremented by 1 is to be used as the context index in accordance with the execution condition code, and carry out the arithmetic decoding process by making use of the determined context index.

Arithmetic decoding apparatus

Disclosed herein is a floating-point number arithmetic circuit for efficiently supplying data to be performed arithmetic operation. The floating-point number arithmetic circuit includes an floating-point number arithmetic unit for performing a predetermined floating-point number arithmetic operation on a floating-point number of a predetermined precision, and a converting circuit for converting data into the floating-point number of predetermined precision and supplying the floating-point number of the predetermined precision to at least either one of input terminals of the floating-point number arithmetic unit.

Floating-point number arithmetic circuit for handling immediate values

Disclosed herein is an arithmetic decoding device including: an arithmetic decoding unit configured to decode coded data resulting from arithmetic coding on a basis of a context variable indicating a probability state and a most probable symbol; a plurality of arithmetic registers configured to supply the context variable to the arithmetic decoding unit and retain a result of operation by the arithmetic decoding unit; and a plurality of save registers configured to save contents retained in the arithmetic registers.

Growing community of inventors

Kanagawa, Japan

Hiroaki Sakaguchi