Fujitsu Corporation

Fujitsu Vlsi Limited

Hiroaki Ogawa

Fumio Baba

Seiji Enomoto

Kazuya Kobayashi

Eisaku Itoh

Masaaki Noguchi

A logic operation circuit includes an instruction signal generating circuit for generating an instruction signal which designates a bit of a predetermined n-bit code signal in accordance with a combination of a first input logical numeral and a second input logical numeral. The logic operation circuit also includes a bit selecting circuit for selecting said bit designated by the instruction signal generated by the instruction signal generating circuit and for outputting the selected bit as an output logical numeral.

Logic operation circuit

A semiconductor memory device includes a RAM and a serial access memory (SAM). The SAM includes an address counter which generates a slave address and a master address. The slave address precedes the master address by half the period of a serial access strobe signal. A redundancy decision is made by comparing the slave address with a redundancy address. When the master address is supplied to a data register provided in the SAM, the decision result is available. That is, the SAM can be accessed immediately after the master address is supplied thereto.

Semiconductor memory device having a serial access memory

A semiconductor memory device having a register and a memory cell array includes a controlling circuit for disconnecting an input/output circuit from a data bus and turning OFF a transfer gate provided between the register and data bus in a first operation mode and for connecting the input/output circuit to the data bus and turning ON the transfer gate in a second operation mode. In the first operation mode, a data read or write operation is performed between the memory cell array and an external circuit, and alternatively in the second operation mode the data read or write operation is performed between the register and the external circuit.

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Nagoya, Japan

Hiroaki Ogawa