University of Tsukuba

Semiconductor Technology Academic Research Center

Kochi University of Technology

Tokai University

Hiroaki Nishikawa

Hiroshi Ishii

Shuji Sannomiya

Ryosuke Kurebayashi

Shinya Ito

Shouhei Nomoto

Keisuke Utsu

Yasuhiro Wabiko

Hiroshi Tomiyasu

Makoto Iwata

In a networking system including a plurality of nodes connected with each other by a communication network, each node includes an abnormality discrimination unit configured, when a cumulative consumption current at the time of processing the data received from other node is out of a range (of current values estimated in advance based on an event at the other node, to discriminate the other node as an abnormal. By the networking system, the abnormality of the nodes on the network may be detected with a simple configuration.

Networking system

The present invention is provided with: a data-driven processor comprising at least a firing control which determines whether or not firing conditions have been met by determining whether or not all packets necessary for instruction execution have been received when a packet that convey a part of partitioned data to be processed has been input, and a data processing unit for performing processing corresponding to the packets transmitted from the firing control if the firing conditions have been met; a power supply circuit for supplying power to the data-driven processor; and overload avoidance means for refusing input of the packets to the data-driven processor, if a determination has been made that a data processing load in the data-driven processor may reach an overloaded state in which the data processing may stall, on the basis of current consumption in the data-driven processor. Accordingly, power consumption in a networking system is reduced.

Ultra low power-data driven networking processing device for avoiding overload

A data processor capable of executing sequential processing efficiently while retaining the advantages of a prior art data-driven processor. The data processor includes: an instruction fetch unit which fetches a data-driven instruction or a control-driven instruction from an instruction memory based on an input packet or a program counter; an instruction decode unit which decodes the issued instruction and, in the case of the control-driven instruction, thereafter accesses a register and performs register renaming if a data hazard is detected; a firing control unit which stores the decoded instruction in a matching memory to wait therein, and which selects one of the ready-to-fire instructions and fires the selected instruction; an execution unit which performs an operation specified by the fired instruction and, in the case of the data-driven instruction, transfers an operation result to the instruction fetch unit, or in the case of the control-driven instruction, forwards the operation result to the firing control unit; and a write back unit which writes the operation result to a register.

Data processor

An emulation system for data-driven processors aims at shortening the emulation time by employing parallel processing techniques without increasing overhead. The emulation system emulates virtual data-driven processors by using real data-driven processors. The emulation is performed by dividing the functionality of the processor into a data path and a timing path. In the data path emulation, each virtual packet to be processed in the virtual processor is expressed as a PACKET message, and the processing operation of the virtual packet is evaluated for each functional block. In the timing path emulation, a SEND signal and an ACK signal, to be controlled by a self-timed transfer control mechanism and a gate logic, are expressed as a SEND message and an ACK message, respectively, and stage-to-stage transfer operations of the SEND signal and the ACK signal are evaluated.

Emulation system for data-driven processor

Growing community of inventors

Tsukuba, Japan

Hiroaki Nishikawa