Mitsubishi Denki Kabushiki Kaisha

Matsushita Electric Industrial Co., Ltd.

Sanyo Electric Co., Ltd.

Sharp Kabushiki Kaisha Corporation

Sharp Corporation

Other

Hiroaki Nishikawa

Hiroaki Terada

Kenji Shima

Hajime Asano

Shinji Komori

Katsuhiko Asada

Masahisa Shimizu

Souichi Miyata

Hiroki Miura

Satoshi Matsumoto

Shuji Hara

Tetsuo Yamasaki

Youichiro Nishikawa

Yoshie Inaoka

Mitsuo Meichi

Isamu Ogawa

Shin-ichi Yoshida

Shunji Hine

Kenji Hamazaki

Kazuhiko Tsugita

Soichi Miyata

Osamu Takahashi

Osamu Ishikawa

Toshiya Okamoto

Koji Shibata

Tetsuya Kobayashi

Kouji Shibata

Tetuya Kobayashi

Isao Masatika

Tadashi Maeda

Moriaki Okuda

Naoki Wada

Katushiko Asada

Yasunori Ieki

Yoshio Sakuta

The discharge lamp lighting apparatus includes: a direct current power supply E; switching elements Q and Q for switching a direct current supplied from the direct current power supply E so as to generate a high frequency current; a discharge lamp load circuit LAC which is constructed in a manner that a discharge lamp LA and a coupling capacitor C are connected in series, and the discharge lamp LA is lit by a high frequency current generated by the switching elements Q and Q ; a switching element control circuit IC for controlling the switching elements Q and Q . The discharge lamp lighting apparatus is further provided with a protective circuit NP which distinguishes a fault of the discharge lamp LA by detecting a voltage generated in the coupling capacitor C , and outputs a control signal to the switching element control circuit IC

Discharge lamp lighting apparatus

A discharge lamp lighting device in which dim control can be performed for a discharge lamp continuously and stably in a wide range, and which is simple in circuit configuration and low in price. The discharge lamp lighting device comprises: an inverter (IV) for turning on/off switching elements (Q,, Q,) by an oscillation output signal of an IV control integrated circuit (IC,) to thereby invert a voltage of a DC power supply (E) into high-frequency electric power, a discharge lamp (LA) capable of being lighted by the high-frequency electric power from the inverter (IV), a feedback circuit (FB) having delay time T (unit: second) expressed by 1/f&lE;T&lE;1/10,000 when the frequency of the high-frequency electric power is f, the feedback circuit (FB) including a reference value setting means (R,) for setting a reference value, the feedback circuit outputting a voltage for controlling the IV control integrated circuit (IC,) to make the high-frequency electric power equal to the reference value.

Discharge lamp lighting device

A file management apparatus includes a file storage portion and a manipulation portion. The file storage portion stores a plurality of files therein. Each file includes one or more data structures. Each data structure includes one or more elements. The file storage portion further identifies each file with a file identifier and identifies each data structure within the file with an internal identifier and with the number of data structures contained in the file. The position of each data element and the number of data elements within a data structure are also identified. The manipulation portion manipulates the structure of the data stored in the file storage portion by employing the file identifier, the data structure identifier, and element position.

File management apparatus permitting access to portions of a file by

A program developing system includes a plurality of graphic editors representing specification definition information a user inputs in representation formats different from each other and a mutual conversion unit for converting specification definition which the user described with a graphic editor into a representation format of another graphic editor. The mutual conversion unit activates another graphic editor to allow input of specification definition by the converted representation format. The graphic editors can hierarchically represent specifications and allows specification description at an arbitrary level. The program developing system includes a parts management unit for registering description of semantically completed specification definition as parts and an execution unit for extracting executable program structure from the specification definition information represented by graphic editors and producing an executable program The executable program reserves the hierarchical structure in the specification description by the user. The execution unit executes a program at an arbitrary level and shows the execution results to the user. By execution and verification of the program at an arbitrary level, the user can know whether a program satisfying the specification is produced or not at a sub program level, which improves the program developing efficiency.

Program developing system allowing a specification definition to be

An associative storage comprises two data transmission paths each of which includes a self-running shift register formed in loop fashion. In the respective data transmission paths, data packets each having identification data are transmitted to respective stages of the shift register. The identification data are extracted from the data packets transmitted on the shift registers and compared with each other in a comparing circuit. If and when the identification data of two data packets respectively transmitted on the respective transmission paths are coincident, those two data packets are determined as the data packets to be paired. The data packet pair is read from the data transmission paths.

Associative storage for data packets including asynchronous,

An apparatus for manipulating a relational data base includes a unit for describing input data in a table format, a unit for describing all the operational manipulation with respect to the input data in a non-text format, and a unit for outputting data by referring to the relational data base based on the described input data and operational manipulation. The input data of a table format includes an input table and an output table. The input table includes an operational description region and the output table includes a region wherein a map relation between the respective items of the input and output table is described. The manipulation contents are described in the operation manipulation description region and the map relation description region. The operation flow is described and defined by a connection line with directiveness. The apparatus enables description of all the operational manipulation in a graphical manner in a non-text format, providing a user with data base manipulation environment with excellent understandability and operability.

Manipulating data in a relational data base having operational

A data transmission apparatus for transmitting data between systems includes: an input data transmission path, an output data transmission path, and a branch data transmission path each constituted by a shift register, each data transmission path has a plurality of data storage circuits and a plurality of transfer control circuits each provided corresponding to each o--stage. The data storage circuit control a self stage data storage circuit in accordance with a control signal from the transfer control circuit of an adjacent stage. An initialization circuit for initializing the device is provided so that data on the data transmission path does not remain at the start of operation of the device.

Data transmission apparatus

By providing a tag data renewing unit in a data flow-computer, the 'delay' function, which is necessary for a digital filter, etc., can be realized, and it is unnecessary to keep the order relation for tokens with respect to first-in/first-out, which must be kept at respective points in a conventional data flow computer, and thereby the architecture of a compiler can be simplified and at the same time the execution time can be shortened.

Information processing apparatus for a data flow computer

A data processing apparatus includes two data transmission paths formed likewise in a loop fashion. These data transmission paths include a plurality of latch registers connected in a cascade fashion respectively and are constituted as a so-called self-running type shift register wherein each data word constituting a data packet is shifted in sequence provided that a pre-stage register is vacant. Data packets are transmitted in the directions reverse to each other on the two loop-shaped data transmission paths an identification data included in each data packet being transmitted is detected in a section defined as a data packet pair detecting section. The detected identification data are compared in a comparing circuit and, one new data packet is produced from the two data packets in a manner that a data packet is joined from one data transmission path to the other data transmission path.

System containing loop shaped transmission paths for transmitting data

In a data transmission apparatus, a plurality of data processing modules are used and required sequence setting is performed to a port sequencer of input/output ports of each data processing module, and the daisy chain transfer of the selective data transfer, the load distribution data transfer, the collective data transfer is combined between the data processing modules, thereby the data transmission is performed efficiently at high speed.

Data transmission apparatus having cascaded data processing modules for

In an information processor, input interface units (161, 162) are connected to one ring data bus (191) through jointing units (201, 202) and data processing units (181 and 185) are connected to the ring data bus (191) through jointing units (203 through 206) and branching units (221 through 224). Data processing units (183 through 187) are connected to the other ring data bus (192) through jointing units (207 through 210) and branching units (225 through 228) and output interface units (171, 172) are connected to the other ring data bus (192) through branching units (229, 230). The ring data buses (191, 192) propagate the respective in data through the input interface units (161, 162) while storing such data, and processing the data in any of the data processing units to provide outputs to any of the output interface units (171, 172). Thus, since the data is transmitted through the ring data buses ( 191, 192) while being held in the data buses, there is no necessity to provide a memory for temporarily storing the data in each data processing unit. In addition, for a large scale integration of a system, it is easy to integrate each unit in a high density.

Information processor capable of data transfer among plural digital data

A data transmission system comprises an input data transmission line (1), an output data transmission line (4), a branching data transmission line (5) and a jointing data transmission line (7) formed respectively by asynchronous free-running shift registers using a plurality of data latches (101 to 106, 401 & 402, 501 & 502, 701 & 702) and, C elements (111 to 116, 411 & 412, 511 & 512, 711 & 712) respectively. A branching control circuit 3 supplies data to be branched to the branching data transmission line (5) in response to the decision by a branching decision circuit (2) as to the fact that the data to be branched is transmitted on the input data transmission line (1). A jointing control circuit (6) supplies data to be joined to the output data transmission line (4) in response to the decision by an empty buffer verifier (8) as to the nonexistence of data in the input data transmission line (1) and the output data transmission line (4) when the data to be jointed is transmitted on the jointing data transmission line (7). Thus, the data transmission system has branching and jointing functions and if it is used as a constituent of a network, data can be transmitted among asynchronous systems.

Data transmission line branching system

A tag data processing apparatus is described for use in a data flow computer utilizing a tagged token scheme. A tag adding process and tag restoring process are executed by using pipeline registers, a queue memory and simple control circuit, thereby obtaining high speed operation and superior throughput without the need for a tag memory table, complicated operation-test circuitry or a sequence control circuit.

Tag Data processing apparatus for a data flow computer

In a data transmission apparatus, a plurality of data processing modules are used and required sequence setting is performed to a port sequencer of input/output ports of each data processing module. The daisy chain transfer of the selective data transfer, the load distribution data transfer, the collective data transfer is combined between the data processing modules, thereby the data transmission is performed efficiently at high speed.

Cascaded information processing module having operation unit, parallel

A simulation method and a computer therefor, i.e., a simulator, for simulating operation of a circuit employing logic gates. The simulation method is to be called the event drive method, in which the output processing is executed only when an input to cause output changes and the output level and the start and finish time for the level are sent out. Hence the number of packets of data flowing for simulation can be minimized and also the number of times of data processing is reduced. This system is applied to each component in a logic circuit, whereby the parallel execution of processing as to the parallel components is possible so as to devise the simulation at a higher speed.

Growing community of inventors

Osaka, Japan

Hiroaki Nishikawa