Kabushiki Kaisha Toshiba

Seiko Epson Corporation

Keio University

Hiroaki Nishi

Atsushi Masuda

Masatoshi Sekine

Yukihito Oowaki

Hideo Shimizu

Kazunori Ohuchi

Takehisa Kato

Takeshi Kitahara

Yoshinori Shigeta

Hiroshige Fujii

Naoki Endo

Masami Aihara

Tsutomu Takei

Hiroyuki Yamashita

Kazuyoshi Kohno

Takanao Amatsubo

Kengo Okada

Takao Shinsha

Tomoya Hirao

Atsushi Ohkuma

Yuichi Nakamura

Michiaki Muraoka

Hideaki Fujikake

Toshiaki Kowatari

An anonymization system is equipped with a provisioning data manager, a provisioning rule manager, and an issuer. Upon receiving data that contains predetermined information and provisioning rules that correspond to the data and are used as conditions under which the data is anonymized, the provisioning data manager stores the data and provides the provisioning rules. The provisioning rule manager stores the provisioning rules provided by the provisioning data manager. When a request is made to issue the anonymized data, that is, the data that has been anonymized, if the issuance request is in accord with the provisioning rules stored in the provisioning rule manager, the issuer acquires the data corresponding to the provisioning rules from the provisioning data manager, issues the anonymized data by anonymizing the acquired data, and provides the anonymized data.

Anonymization system, issuance device, and storage medium

A behavioral synthesis apparatus includes a control data flow graph generator that generates a CDFG specifying an execution order of calculations written in a behavior description including an external loop processing that includes internal loops processing which does not expand the internal loops processing, a scheduling module carries out scheduling of calculations, and an assigning module divides first pipeline processing for implementing the external loop processing and second pipeline processing for implementing the internal loops processing into stages, and assigns pipeline registers to the external loop processing and the internal loops processing.

Apparatus, method and program for behavioral synthesis including loop processing

A hardware/software co-verification method that achieves fast simulation execution by implementing a C-based native code simulation without degrading the accuracy of timing verification. This method is a method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted wherein, first, a timed software component described in a C-based language or constructed from binary code native to the host CPU and a hardware component described in the C-based language are input as verification models, necessary compiling is performed, and the compiled components are linked together. Next, a testbench is input and compiled. Then, the components and the testbench are linked together, after which simulation is performed and the result of the simulation is output.

Method for co-verifying hardware and software for a semiconductor device

A semiconductor integrated circuit for cryptographic process according to the present invention, comprises a randomizing unit for randomizing first input data which is one of two divided parts of input data based on configuration information to identify an algorithm in randomizing process, a function F portion for receiving data which have been subjected to the randomizing process and then applying coding process to the data, and an exclusive logical sum circuit for receiving second input data which is other of two divided parts of the input data and output data from the function F portion and then outputting an exclusive logical sum of the second input data and the output data.

Semiconductor integrated circuit for cryptographic process and encryption algorithm alternating method

A model of architecture of a processor is called an architecture template. Because a designer selects an architecture template of a special purpose processor which is suitable for an objective signal processing algorithm from an architecture template library, a special purpose processor which is the most suitable for any signal algorithm can be synthesized. Moreover, by providing a method of creating an architecture template simply, even if there is no desirable architecture template, an objective architecture template can be synthesized for a short time.

Logical circuit automatical design method and system, and computer

Disclosed is a test assistant system for a logical design process comprising a description storage data base for storing statements expressing logical functions of circuit components to be tested, a compiler for compiling the statements to output object data, a data base for storing the object data, a test pattern generator for generating test patterns by using the object data stored in the data base, a test pattern data base for storing the test patterns, each having a level number, a simulator for executing a simulation for the logical function by using the test patterns stored in the test pattern data base, and a display for displaying the object data, the test patterns, the information used in the simulation, and relationships among them. The data base comprises a region for storing a statement correspondence table expressing statements as descriptions of the logical functions of the circuit components, a region for storing a circuit component table expressing a circuit component corresponding to the function described in the statement, a region for storing a dependent relationship table expressing the dependent relationship between the statements, and a correspondence relationship table expressing the correspondence relationship between the statement correspondence table and the circuit component table.

Test assistant system for logical design process

Disclosed is an integrated semiconductor circuit device which has a plurality of cell arrays formed in parallel on a surface region of the substrate, and a three-layer wire formed on the substrate and between each cell array. The direction of a wire track of a second layer wire is originally determined in a direction parallel to the cell arrays, and the direction of wire tracks of first and third layer wires is originally determined in a direction orthogonal to the originally determined direction of the wire track of the second layer wire. The first layer wire and the third layer wire are formed on the same wire track. Part of the third layer wire is formed on a wire track orthogonal to the originally determined direction of the wire track of the third layer, and the third layer wire and the second layer wire are connected to each other on the wire track which is orthogonal to the originally determined direction of the wire track of the third layer wire.

Integrated semiconductor circuit device

Growing community of inventors

Kanagawa, Japan

Hiroaki Nishi