Texas Instruments Corporation

Globalfoundries Inc.

International Business Machines Corporation

Tokyo Electron Limited

The State University of New York

Hiroaki Niimi

Tenko Yamashita

James Joseph Chambers

Husam N Alshareef

Shogo Mochizuki

Oleg Gluschenkov

Zuoguang Liu

Haowen Bu

Manoj Mehrotra

Malcolm John Bevan

Ruilong Xie

Rajesh B Khamankar

Steven J Bentley

Mahalingam Nandakumar

Chun-chen Yeh

Reima Tapani Laaksonen

Douglas Ticknor Grider

Kwan-Yong Lim

Rick L Wise

Shariq Siddiqui

Brent A Anderson

Takashi Ando

Brian Keith Kirkpatrick

Jarvis Benjamin Jacobs

Puneet Harischandra Suvarna

Ajith Varghese

Junli Wang

Julien Frougier

Luigi Colombo

Daniel Chanemougame

Kandabara N Tapily

Jody Alan Fronheiser

Sunil V Hattangady

Toan Tran

April Gurba

Charles Frank Machala, Iii

Jiseok Kim

Kangguo Cheng

Vijay Narayanan

Balasubramanian Pranatharthiharan

Min Gyu Sung

Hoon Sik Kim

Huiming Bu

Muthumanickam Sankarapandian

Gerrit J Leusink

Mark V Raymond

Seung-Chul Song

Ali Razavieh

Yun Han

Manuel A Quevedo-Lopez

Takahiro Hakamata

Huang-Chun Wen

Gyanaranjan Pattanaik

Kwanyong Lim

Joseph S Washington

Hui-feng Li

John H Zhang

Lars W Liebmann

Anton J deVillers

Naoki Watanabe

Alok Ranjan

Kisik Choi

Guillaume Bouche

Jeffrey Smith

Robert Daniel Clark

Xusheng Kevin Wu

Christopher Joseph Waskiewicz

Michael P Belyansky

Andy C Wei

Tatsuo Matsudo

Peter Ventzek

Antonio L P Rotondaro

Andrew W Metz

Andreas Knorr

Einstein Noel Abarra

Pietro Montanini

Cory Wajda

Kai-Hung Yu

Subhadeep Kal

Takuya Sugawara

Eric Chih-Fang Liu

Nigel Graeme Cave

Jodi Grzeskowiak

Hiroki Maehara

Shihsheng Chang

Henan Zhang

Romain Lallement

Ying Trickett

Elisabeth Marley

Koji Shimomura

Manoj Mehortra

A method of forming a metal superlattice structure includes depositing, on a substrate, a layer of a first metal with face-centered-cubic (fcc) crystal structure. The method further includes depositing a layer of ruthenium (Ru) metal with fcc crystal structure on the layer of the first metal. The layer of the first metal may cause the layer of ruthenium metal to have fcc crystal structure.

Conductive superlattice structures and methods of forming the same

A method for manufacturing a FET semiconductor structure includes providing a substrate comprising at least one source/drain contact of at least one FET, the at least one source/drain contact formed adjacent to a dummy gate of the at least one FET. A TiSifilm with C54 structure is selectively deposited directly on and fully covering the at least one source/drain contact relative to a vertical sidewall of a gate spacer between the at least one source/drain contact and the dummy gate. The dummy gate is replaced with a replacement metal gate.

Method of forming a FET structure by selective deposition of film on source/drain contact

A semiconductor device includes a first raised feature in a NFET region on a substrate, a first n-type doped epitaxial semiconductor material grown on the first raised feature, the first n-type doped epitaxial material having a first upward facing surface and a first downward facing surface, a first contact metal on the first downward facing surface, and a second contact metal on the first upward facing surface. The device further includes a second raised feature in a PFET region on the substrate, a second p-type doped epitaxial semiconductor material grown on the second raised feature, the second p-type doped epitaxial material having a second upward facing surface and a second downward facing surface, a third contact metal on the second downward facing surface, and a fourth contact metal on the second upward facing surface, wherein the fourth contact metal is different from the second contact metal.

Dual metal wrap-around contacts for semiconductor devices

A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.

Method for filling recessed features in semiconductor devices with a low-resistivity metal

Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5&#xd7;10atoms per cubic centimeter (at./cm). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

Low resistance source drain contact formation with trench metastable alloys and laser annealing

A first source/drain (S/D) structure of a first transistor is formed on a substrate and positioned at a first end of a first channel structure of the first transistor. A first substitute silicide layer is deposited on a surface of the first S/D structure and made of a first dielectric. A second dielectric is formed to cover the first substitute silicide layer and the first S/D structure. A first interconnect opening is formed subsequently in the second dielectric to uncover the first substitute silicide layer. The first interconnect opening is filled with a first substitute interconnect layer, where the first substitute interconnect layer is made of a third dielectric. Further, a thermal processing of the substrate is executed. The first substitute interconnect layer and the first substitute silicide layer are removed. A first silicide layer is formed on the surfaces of the first S/D structure.

Reverse contact and silicide process for three-dimensional logic devices

Embodiments of the present invention are directed to techniques for forming a robust low-k bottom spacer for a vertical field effect transistor (VFET) using a spacer first, shallow trench isolation last process integration. In a non-limiting embodiment of the invention, a semiconductor fin is formed over a substrate. A first dielectric liner is formed on a sidewall of the semiconductor fin. A bottom spacer is formed over the substrate and on a sidewall of the first dielectric liner. The first dielectric liner is positioned between the semiconductor fin and the bottom spacer. Portions of the bottom spacer are removed to define a shallow trench isolation region.

Robust low-k bottom spacer for VFET

A semiconductor device and a method of forming a semiconductor device. The semiconductor device includes a first raised feature in a n-type channel field effect transistor (NFET) region on a substrate, a first doped epitaxial semiconductor material grown on the first raised feature, a first metal contact on the first doped epitaxial semiconductor material, a first metal nitride on the first metal contact, and a first ruthenium (Ru) metal plug on the first metal nitride. The device further includes a second raised feature in a p-type channel field effect transistor (PFET) region on the substrate, a second doped epitaxial semiconductor material grown on the second raised feature, a second metal contact on the second doped epitaxial semiconductor material, a second metal nitride on the second metal contact, and a second ruthenium (Ru) metal plug on the second metal nitride.

Dual metal contacts with ruthenium metal plugs for semiconductor devices

An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

High mobility transistors

An integrated semiconductor device having a substrate and a vertical field-effect transistor (FET) disposed on the substrate. The vertical FET includes a fin and a bottom spacer. The bottom spacer further includes a first spacer layer and a second spacer layer formed on top of the first spacer layer. The bottom spacer provides for a symmetrical straight alignment at a bottom junction between the bottom spacer and the fin.

Transistor having straight bottom spacers

A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal.

Replacement metal gate process for CMOS integrated circuits

Aspects of the present invention relate to approaches for forming a narrow source-drain contact in a semiconductor device. A contact trench can be etched to a source-drain region of the semiconductor device. A titanium liner can be deposited in this contact trench such that it covers substantially an entirety of the bottom and walls of the contact trench. An x-metal layer can be deposited over the titanium liner on the bottom of the contact trench. A titanium nitride liner can then be formed on the walls of the contact trench. The x-metal layer prevents the nitriding of the titanium liner on the bottom of the contact trench during the formation of the nitride liner.

Titanium silicide formation in a narrow source-drain contact

A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.

Dual metal-insulator-semiconductor contact structure and formulation method

An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.

Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts

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Cohoes, NY, United States of America

Hiroaki Niimi