Hitachi, Ltd.

Hitachi Engineering Co., Ltd.

Hitachi Process Computer Engineering, Inc.

Hitachi Process Engineering, Inc.

Hiroaki Nakanishi

Tadaaki Bandoh

Hidekazu Matsumoto

Shinichiro Yamaguchi

Kenji Hirose

Keiichi Nakane

Yoshiki Kobayashi

Yoshihiro Miyazaki

Jushi Ide

Hirokazu Hirayama

Takeshi Kato

Hideo Maejima

Masahiko Saito

Yasushi Fukunaga

Hirokazu Kasashima

Takanori Yokoyama

Kotaro Hirasawa

Koji Hirai

Tomoaki Nakamura

Masahiro Kainaga

Tadashi Kamiwaki

Masakazu Okada

Yoshiaki Adachi

Hiroshi Wataya

Takeshi Katoh

Toshiro Kamiuchi

Hiroyuki Hori

Kousuke Sakoda

Masaru Shimada

Hideyuki Hara

Takayuki Morioka

Ryosei Hiraoka

Takao Kobayashi

Hideki Tonooka

Hiroshi Kobayashi

Tetsuya Kawakami

Hideki Sato

Teruyasu Nakahashi

Keiichi Sannomiya

Ryoichi Takamatsu

Toshimasa Saika

Isao Terakado

Tsutomu Onuki

Kenji Matsuzaki

Keijiro Hayashi

Shigeru Endo

Shuji Nishiyama

Tomohito Ebina

Shimako Tanno

Toshihisa Oka

Kenzi Hirose

A computer system is so configured as to be divided into a control system which should have high reliability and high responsiveness and an information system which does not access the control system. They are connected via a transmission path (transmission path of control system and transmission path of information system). Centralized management of development and maintenance is performed from a software maintenance system. In development and maintenance of software, management according to the feature of each software such as processing contents of each software, demanded reliability, and version up frequency is performed from a maintenance system for exclusive use by using a transmission path of information system. Thereby, development and maintenance having high reliability and expandability is realized.

System for software update in manner based on processing properties of

There is disclosed an information processing system and method capable of coping with a wider range of subjects and intricate changes. In client server structure, time-varying database altering information received from external systems is pooled in servers and distributed to a number of distributed terminals or clients, using broadcasting communication.

Information processing system and method using time-varying database

A distributed processing system capable of realizing efficient management of a multiplicity of objects in a large scale distributed processing comprises an objectification unit which makes it possible to handle an assembly of objects as one object and a message transfer unit by which a request for a processing to one object provided by objectification by the objectification unit is made to an optimal one of plural objects subjected to objectification.

Distributed processing system for modules, each having modularized

A data processor for execution of tagged data and tagless data has a decoder for discriminating whether the data is tagged or tagless one and in case of a tagged data, separates a tag part and uses the remaining part for address computation. The data processor also comprises a unit for evaluating the tag part and a micro program controller for multi-branching in accordance with the evaluation result of the tag part. The tag evaluating unit includes an extender eliminating part for extracting the tag part from data on a data bus, a plurality of tag part storing registers for storing the tag part from the eliminating part under the control of the micro program controller, and a tag multi-way jump encoder for generating a tag multi-way jump address to feed it to the controller on the basis of the outputs of the registers and a signal from the micro program controller, thereby enabling tag multi-way jump.

Data processor provided with instructions which refer to both tagged and

An operation unit capable of performing round processing at a high speed in a floating point operation. A circuit for detecting an overflow on the condition of a signal representing all 1's in an output of a mantissa shifter and a signal representing round-up, a carry look-ahead circuit and a circuit for generating a round precision signal are provided. When the overflow takes place, the mantissa is produced as '1'. The operation unit is compatible to single, double and extended precisions recommended by Institute of Electrical and Electronic Engineers (IEEE).

Apparatus for performing floating point arithmetic operations and

A bit slice multiplication circuit operating to slice a multiplier, produce products for the sliced multipliers and a multiplicand and sum the products to obtain the multiplication result. The circuit includes a slicing unit for slicing the multiplicand, multiplying units corresponding in number to the number of sliced multiplicands, and adding units provided in correspondence to the multiplying units and implementing summation for multiplication results from corresponding multiplying units while shifting the sliced portions of the multiplicand at each multiplying operation for sliced multipliers and multiplicands by the multiplying units, the multiplication result being obtained by summing all summation results produced by the adding units.

Bit slice multiplication circuit

A multicomputer system having dual common memories in which specified address areas are set within the common memories. The specified address areas are accessible irrespective of whether a CPU is in an online mode or a debug mode, while any area other than the specified address areas is accessible only when the function mode of the common memory is in agreement with the access mode of the CPU. In correspondence with each CPU, addresses to be used by the CPU are divided into a plurality of groups of addresses, and the access modes are set for the respective address groups.

Multicomputer system having dual common memories

A virtual storage managing system in which the storage address is managed by means of a virtual address, and the virtual storage area which can be assigned by the virtual address is divided into an address non-translation area which does not require the address translation and an address translation system which requires an address translation. The address translation area is divided into an address fixed area and an address variable area. In the address translation area, the correspondence between the virtual address and the real address is fixed in a 1:1 fashion, whereas, in the address variable area, the correspondence is determined at the time of starting of execution of a program and is dismissed when the execution of the program is completed.

Virtual storage management

A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flat is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.

Central processing unit for executing instructions of variable length

An operating system (OS) is divided into units (OS processes) which are concurrently executable. When the processors concurrently request the execution of one OS process, data indicating that the requested OS process is in a ready state is loaded into a memory. The other processors repeatedly make an access to the data during the course of the execution of the user's task to check to see whether the ready-state OS process is present or not. A processor when detecting the ready-state OS process ceases the execution of the user's program and executes that OS process.

Method of processing an operating system in a multi-processor system

A data processing system having a first storage for storing therein microprograms; an address register for supplying an instruction address of a microprogram to be executed into said first storage; a stack unit having a stack area for storing therein a return address of the microprogram; a first control unit responsive to a microinstruction for instructing a microsubroutine call to store the return address of the microinstruction in the stack unit, and responsive to a microinstruction for instructing return from the microsubroutine to restore the return address of the microinstruction from said stack unit; a second control unit for monitoring an interrupt request; a second storage for saving therein the content of said stack unit; a status register having a field for indicating the acceptance of the interrupt request in the course of the execution of the microprogram, and a third control unit responsive to the detection of the interrupt request by the second control unit in the course of the execution of the microprogram to indicate the acceptance of the interrupt request by the status register and save the content of the stack unit in said second storage, and responsive to the presence of the indication in the status register indicating the acceptance of the interrupt request at the end of the execution of an interrupt processing program to restore the content of the second storage to said stack unit.

Data processing system with improved microsubroutine facility

A multi-computer system having a dual common memory adapted to perform Read/Write operations by means of a plurality of computers. Each computer in the system consists of a central processing unit, a main memory and a dual memory access unit. The dual memory access unit is adapted to provide a status signal representative of whether the data from the common memory is correct or not and a maintenance signal representative of whether a maintenance operation is demanded. A memory access is made only to the common memory demanding the maintenance when the program run by the computer is a maintenance program, and only to the normal common memory during the usual operation.

Multi-computer system having dual common memory

A multi-computer system includes a plurality of data processors and at least one I/O device which is commonly accessible by the data processors. A plurality of serial bus loops are configurated in hierarchy with interbus linkage devices disposed between adjacent layers of the hierarchy. The data processors are connected to a plurality of first layer serial bus loops and the I/O device which is commonly accessible by the data processors is connected to a second layer of serial bus loop. The interbus linkage devices control linkage among the plurality of serial bus loops and carry out routing control for a start command from the data processor to the I/O device, routing control for an interruption to report the end of I/O device operation, routing control for data transfer, routing control for a request interruption and exclusive use control of the shared I/O device.

Multi-computer system with plural serial bus loops

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Hitachi, Japan

Hiroaki Nakanishi