Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Hiroaki Muraoka

Takaya Suda

Hironori Sato

Toshiyuki Miyashita

A device for automatic configuration of a semiconductor integrated circuit includes a memory that stores circuit data representing a structure of a logic circuit including a first clock gating circuit, and a processor. The processor is configured to retrieve the circuit data from the memory, determine first and second logical elements from each of which an enable signal is output to the first clock gating circuit, calculate a delay time of each of the first and second logical elements, separate the first and second logical elements on the basis of the calculated delay time, and add a second clock gating circuit for the first logical element after separating the first and second logical elements.

Device for automatic configuration of semiconductor integrated circuit

A memory controller includes a first calculation circuit configured to calculate an intermediate calculated value of an error correction code by using the head byte to a specified byte of a data in a process of calculating the error correction code for the data read from a memory, a data storage circuit configured to store the intermediate calculated value, a changing circuit configured to change data in a following part of the specified byte of the data, a second calculation circuit configured to calculate another error correction code by using the intermediate calculated value and the data in the following part including the changed data, and a data transferring circuit configured to transfer the changed data and the error correction code calculated in the second calculation circuit to the memory.

Memory controller

A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device comprises a setting unit configured to set an address range of data to be erased in response to an erase command in a block in which the data to be erased is written, when the erase command is issued with respect to the nonvolatile semiconductor memory and a controlling unit configured to output initial-value data as data to be read in response to a data read command, when the data read command is issued with respect to the nonvolatile semiconductor memory, and then when an address range of the data to be read in response to the data read command is included in the address range set by the setting unit.

Memory management device and memory device

Described herein is a dynamic latch circuit having a pair of control terminals connected to receive complementary first and second control clock pulses which are generated at a predetermined frequency, and a register section for detecting the voltage of an input signal, in response to each of the first and second control clock pulses, and generating an output signal from a capacitive output node which is charged or discharged in accordance with the voltage of the input signal and is subsequently set at a low potential or a high potential. The latch circuit further comprises a voltage-generating circuit for detecting, based on a period of time elapsed from the trailing edge of the last generated first control clock pulse, that the supply of the first control clock pulses has been stopped and fixedly setting the output node at the low potential.

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Kamakura, Japan

Hiroaki Muraoka