Sony Corporation

Hiroaki Miyachi

Jun Iwasaki

Satoshi Konya

Nobuo Namekawa

Tomonari Yamagata

Masaru Goto

Yukihiro Sakamoto

A communication apparatus, a communication system, a communication method, and a program capable of performing relay transfer of a data file swiftly and simply in performing short-distance one-to-one communication are provided. The communication apparatus includes a communication part that performs short-distance one-to-one communication with a communication partner apparatus via electric field coupling or magnetic field coupling, a relay transfer mode setting part that sets a relay transfer mode in which a data file are relay-transferred from at least one first apparatus to at least one second apparatus, a storage part that holds the data file received from the first apparatus while the relay transfer mode is set, and a transmission control part that transmits the data file held in the storage part to the second apparatus with which communication is established while the relay transfer mode is set.

Communication apparatus, communication system, communication method, and program

A communication apparatus of the present invention includes a transmission/reception coupler for performing a one-to-one communication at short distance with an apparatus of a communication opponent by electric field coupling or magnetic field coupling; a plural copy mode setting unit for setting a plural copy mode for transferring a data file to a plurality of apparatuses; a data file selecting unit for selecting a data file to transfer to the plurality of apparatuses; a file transfer processing unit for transferring the data file already selected in the data file selecting unit to an apparatus, which communication is established, when the plural copy mode is set; and a plural copy mode canceling unit for canceling the plural copy mode.

A 32-bit RISC processor is disclosed. The bit length of the instruction set is fixed to 16 bits. SLIL and SLIH instructions that cause the address space of 4 Gbytes to be limited to upper 2 Mbytes and that execute a long type register branch instruction are provided. Thus, a register branch instruction can be executed with three instructions rather than five instructions unlike with a related art reference.

Microprocessor with reduced instruction set limiting the address space to upper 2 Mbytes and executing a long type register branch instruction in three intermediate instructions

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Tokyo, Japan

Hiroaki Miyachi