J-Devices Corporation

Oki Electric Industry Co., Ltd.

Hiroaki Matsubara

Tomoshige Chikai

Shingo Nakamura

Takeshi Miyakoshi

Shotaro Sakumoto

Sumikazu Hosoyamada

Yoshikazu Kumagaya

Toshihiro Iwasaki

Kiminori Ishido

Shinji Watanabe

Hirokazu Honda

Michiaki Tamakawa

Takashi Nakamura

Hiroshi Demachi

Hiroshi Inoue

Naoki Hayashi

Yoshihiko Ikemoto

Yukari Imaizumi

Yoshihisa Nakamura

Koichiro Niwa

A semiconductor device includes a lead frame; a circuit board located on the lead frame; a power device that includes a switching element and is mounted on the circuit board via a bump located between the power device and the circuit board; and a heat releasing member connected to the power device. The circuit board may be a multi-layer wiring board. The circuit board may include a capacitor element, a resistor element, an inductor element, a diode element and a switching element.

Semiconductor device

A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.

Semiconductor package

An interconnect structure in which the current capacity of an interconnect pattern involving a large amount of current is increased without preventing the miniaturization of signal lines and increasing the film thickness. The interconnect structure includes a resin layer; and interconnects formed on the resin layer, wherein the resin layer has a plurality of parallel grooves in an area in which the interconnects are formed, and the interconnects are formed of a plating film created on a resin layer front surface in the area, in which the interconnects are formed, and on inner wall surfaces of the plurality of grooves.

Interconnect structure, printed circuit board, semiconductor device, and manufacturing method for interconnect structure

A semiconductor device including: a support plate; a semiconductor chipmounted on one principal surface of the support platevia an adhesive layer, with the element circuit surface of the chip being directed upward; an insulation material layerthat seals the semiconductor chipand the periphery of the semiconductor chip; openings formed on an electrode arranged on the element circuit surface of the semiconductor chipin the insulation material layer; conductive portionsformed in the openings so as to be connected to the electrode of the semiconductor chip; a wiring layerformed on the insulation material layerso as to be connected to the conductive portionsand partially extending to the peripheral region of the semiconductor chip; and external electrodesformed on the wiring layer

Semiconductor device and method of manufacturing semiconductor device

A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.

A magnetic shielding package of a non-volatile magnetic memory element, including: a soft magnetic material support plate; a first insulating material layerformed on the support plate; a non-volatile magnetic memory elementfixed on the first insulating material layer; a second insulating material layerthat encapsulates the memory element and the periphery thereof; in the second insulating material layer, a wiring layer, a soft magnetic layerorand a conductive portionconnecting an electrode of the circuit surface of the memory element and the wiring layer; and a magnetic shield partcontaining a soft magnetic material arranged like a wall at a distance from a side surface of the memory element so as to surround the memory element side surface partially or entirely, the magnetic shield part being magnetically connected to the soft magnetic layer.

Magnetic shielding package of non-volatile magnetic memory element

A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thickness.

Manufacturing method for semiconductor device

A semiconductor package includes a support substrate arranged with a first aperture reaching a semiconductor device on a rear side, the semiconductor device is bonded via an adhesive to a surface of the support substrate, an insulating layer covering the semiconductor device, and wiring for connecting the semiconductor device and an external terminal through the insulating layer. The adhesive may form a part of the first aperture. In addition, a heat dissipation part may be arranged in the first aperture and a metal material may be filled in the first aperture.

Heat sink in the aperture of substrate

A speech synthesizer includes a data memory having a plurality of address areas, which stores a plurality of phases in the address areas and an address designating circuit designating one of the address areas based on the phase signal. Further, a speech synthesizer includes a speech synthesizing circuit generating a speech synthesizing signal corresponding to the phase, which is stored in the designated area, a digital/analog converter transforming the speech synthesizing signal to an analog signal having amplitude, and a counter setting a period of silence. Furthermore, a speech synthesizer includes a silence-input circuit being connected between the speech synthesizing circuit and the digital/analog converter, which supplies a predetermined voltage to the digital/analog converter for the period that is set by the counter.

Speech synthesizer that interrupts audio output to provide pause/silence between words

A signal-generating circuit receives a program signal and generates an output enable signal, a control signal, and a latch signal. In response to the output enable signal, a programmable read-only memory outputs data onto a data bus. In response to the control signal, a three-state buffer outputs data from a first register to the data bus; the data can then be stored in the programmable read-only memory by input of a chip enable signal. In response to the latch signal, a second register latches data output from the programmable read-only memory onto the data bus. An equality checker compares the contents of the first and second registers and generates an equal signal indicating whether they are equal.

Growing community of inventors

Kanagawa, Japan

Hiroaki Matsubara