Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Hiroaki Maekawa

Megumi Yakabe

Yuichi Ohsawa

Minoru Amano

Eiji Kitagawa

Chikayoshi Kamata

Daisuke Saida

Naoharu Shimomura

Kazutaka Ikegami

Saori Kashiwada

Kazuyo Ishii

A reliability evaluation apparatus according to the present embodiment is provided with a housing and a board insertable into the housing. A plurality of sockets are provided on the board. Semiconductor devices are respectively attachable to socket. The plurality of sockets have electrodes electrically connectable to terminals of the semiconductor devices. A heater is provided inside the housing. A controller is connected to the plurality of sockets and to the heater. The controller controls a voltage to be applied to the terminal of the semiconductor device and controls an output of the heater. A plurality of electromagnets are arranged inside the housing so as to be positioned above or below the plurality of sockets when the board is inserted into the housing.

Reliability evaluation apparatus

A semiconductor storage device includes a plurality of first memory elements in a first region and a plurality of second memory elements in a second region. The second memory elements each have a physical volume that is greater than a physical volume of the first memory elements. A controller is configured to first write data to the plurality of first memory elements and then transfer the data written to plurality of first memory elements to the plurality of second memory elements when at least one of an elapsed time since initial writing or a data reading frequency exceeds a threshold value. In general, the first memory elements and the second memory elements are variable resistance elements.

Semiconductor storage device

A magnetoresistive element according to an embodiment includes: a multilayer structure including a first magnetic layer, a second magnetic layer disposed above the first magnetic layer, and a nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a conductor disposed above the second magnetic layer, and including a lower face, an upper face opposing to the lower face, and a side face that is different from the lower face and the upper face, an area of the lower face of the conductor being smaller than an area of the upper face of the conductor, and smaller than an area of an upper face of the second magnetic layer; and a carbon-containing layer disposed on the side face of the conductor.

Magnetoresistive element and magnetic memory

A magnetoresistive effect element includes a recording layer having magnetic anisotropy and a variable magnetization direction, a reference layer having magnetic anisotropy and an invariable magnetization direction, an intermediate layer between the recording layer and the reference layer, an underlayer containing scandium (Sc) and disposed on a surface side of the recording layer opposite to a surface side on which the recording layer is disposed, and a side wall layer containing an oxide of Sc and disposed on side surfaces of the recording layer and the intermediate layer.

Magnetoresistive effect element having an underlayer and a side wall layer that contain scandium

According to one embodiment, a magnetic memory includes a first magnetoresistive element includes a storage layer with a perpendicular and variable magnetization, a tunnel barrier layer, and a reference layer with a perpendicular and invariable magnetization, and stacked in order thereof in a first direction, and a first shift corrective layer with a perpendicular and invariable magnetization, the first shift corrective layer and the storage layer arranged in a direction intersecting with the first direction. Magnetization directions of the reference layer and the first shift corrective layer are the same.

Growing community of inventors

Yokohama Kanagawa, Japan

Hiroaki Maekawa