Tower Partners Semiconductor Co., Ltd.

Tower Semiconductor Ltd.

Hiroaki Kuriyama

Hiroshige Hirano

Yakov Roizin

Takayuki Yamada

Erez Sarig

Masahiko Sakagami

Micha Gutman

Kenji Tateiwa

Atsushi Noma

A semiconductor device includes a memory cell on a semiconductor substrate. The memory cell includes a memory element, a first assistance element, and a second assistance element. The memory element includes a source region and a drain region, and a selection gate and a floating gate in series therebetween. The first assistance element includes a first impurity region and a first gate. The second assistance element includes a second impurity region and a second gate. The first and second gates are electrically connected to the floating gate. The second impurity region is connected to a signal line that is connected to the drain region or a signal line that is connected to the selection gate.

Semiconductor device having a memory element with a source region and drain region and having multiple assistance elements

A semiconductor device includes a storage element write unit including a storage element configured to be electrically written only once and store two values, a write controller connected to the storage element through a first node signal and configured to perform a write to the storage element based on a write control signal instructing a write to the storage element, and a write state detection circuit configured to detect that the storage element is in a write state based on a measurement signal obtained by measuring the first node signal. In a case where the write controller receives a detection signal indicating that the storage element is in the write state from the write state detection circuit after start of a write to the storage element, the write controller stops write operation after a lapse of a predetermined time from detection of the write state of the storage element.

Semiconductor device for writing to a storage element

First and second memory cells are arranged on a semiconductor substrate. The memory cell includes, between a first or second source region and a first or second drain, a configuration in which a first or second selection gate and a first or second floating gate are arranged in series. The first memory cell and the second memory cell are adjacent to each other in a first direction. A first signal line extending in the first direction and connected to the first and second selection gates is further provided. The first and second source regions are configured to share a first region. The first selection gate extends in a direction different from the first direction.

Semiconductor device

An active region includes a body region in which first and second transistors are formed, a connection portion to which a potential of the body region is connected, and a lead portion that connects the body region and the connection portion. Source regions or drain regions of the first and second transistors formed in the body region are provided in a common region. Each of the lead portions extends from a corresponding channel region such that the lead portions are isolated from each other, and a gate electrode extends thereon. A width of the lead portion is narrower than a distance between corresponding ones of contact portions of the source regions and the drain regions of the first and second transistors. A width of the connection portion is equal to or narrower than a gate width of the gate electrode extending on the lead portion.

A semiconductor device includes a memory cell formed on a semiconductor substrate. The memory cell includes a first source region and a first drain region that are formed in the semiconductor substrate and a first selection gate, and a first floating gate disposed in series between the first source region and the first drain region. A first floating gate transistor including the first drain region and the first floating gate has a threshold set lower than a threshold of a first selection gate transistor including the first source region and the first selection gate.

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Toyama, Japan

Hiroaki Kuriyama