Spansion Llc.

Monterey Research, LLC

Hiroaki Kouketsu

Masaya Hosaka

Masahiko Higashi

A semiconductor device includes a semiconductor substrate, an ONO (oxide/nitride/oxide) film provided on the semiconductor substrate, a control gate provided on the ONO film, a first low-resistance layer, and a second low-resistance layer in contact with the first low-resistance layer, the second low-resistance layer having a sheet resistance lower than the first low-resistance layer. With this configuration, it is possible to downsize the memory cell and provide a fabrication method of the semiconductor device in which the peripheral circuit can be fabricated with simple fabrication processes.

Semiconductor memory device having lowered bit line resistance

A semiconductor device is provided which includes a gate electrode () provided on a semiconductor substrate (), an oxide/nitride/oxide (ONO) film () that is formed between the gate electrode () and the semiconductor substrate () and has a charge storage region () under the gate electrode (), and a bit line () that is buried in the semiconductor substrate () and includes a low concentration diffusion region (), a high concentration diffusion region () that is formed in the center of the low concentration diffusion region () and has a higher impurity concentration than the low concentration region, a source region, and a drain region. The semiconductor device can improve the source-drain breakdown voltage of the transistor while suppressing fluctuation of electrical characteristics or junction current between the bit line () and the semiconductor substrate ().

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Aizuwakamatsu, Japan

Hiroaki Kouketsu