Fuji Electric Co., Ltd.

Hiroaki Ichikawa

Mitsuhiro Kakefu

Shuangching Chen

Akio Yamano

Taichi Itoh

Aiko Takasaki

Takuya Yamamoto

A drive device for driving a voltage-controlled semiconductor element. The drive device includes: a drive circuit connected to the gate of the semiconductor element via a gate resistor; a delay circuit connected to the drive circuit, for delaying a drive signal output from the drive circuit until a gate voltage of the semiconductor element enters a Miller effect period, which is a period during which the gate voltage transitionally changes, the gate voltage having temperature dependency on a chip temperature of the semiconductor element; a one-shot circuit connected to the delay circuit, for outputting a pulse signal with a pulse width shorter than the Miller effect period; a comparator that compares the gate voltage with a reference voltage; and an AND circuit that outputs an overheat detection signal in response to the gate voltage exceeding the reference voltage.

Drive device for voltage-controlled semiconductor element

A semiconductor device including a semiconductor unit that has a first arm part, which includes: first and second semiconductor chips having first and second control electrodes on their front surfaces, a first circuit pattern where the first and second semiconductor chips are disposed, a second circuit pattern to which the first and second control electrodes are connected, and a first control wire electrically connecting the first and second control electrodes and the second circuit pattern sequentially in a direction; and a second arm part, which includes third and fourth semiconductor chips having third and fourth control electrodes on their front surfaces, a third circuit pattern where the third and fourth semiconductor chips are disposed, a fourth circuit pattern to which the third and fourth control electrodes are connected, and a second control wire electrically connecting the third and fourth control electrodes and the fourth circuit pattern sequentially in the direction.

Semiconductor device

A semiconductor device, having a first semiconductor chip including a first side portion at a front surface thereof and a first control electrode formed in the first side portion, a second semiconductor chip including a second side portion at a front surface thereof and a second control electrode formed in the second side portion, a first circuit pattern, on which the first semiconductor chip and the second semiconductor chip are disposed, a second circuit pattern, and a first control wire electrically connecting the first control electrode, the second control electrode, and the second circuit pattern. The first side portion and the second side portion are aligned. The first control electrode and the second control electrode are aligned. The second circuit pattern are aligned with the first control electrode and the second control electrode.

A semiconductor device having an arm block. The arm block includes a first circuit pattern that, in a plan view of the semiconductor device, has a recess formed thereon that extends inward from a side thereof, the recess forming a disposition area of the semiconductor device, a second circuit pattern having at least a part disposed in the disposition area, and a plurality of semiconductor chips formed on the first circuit pattern. Each semiconductor chip has a positive electrode on a back surface thereof, and a control electrode and a negative electrode on a front surface thereof, the negative electrode being electrically connected to the second circuit pattern by a wiring member.

A semiconductor device is provided to reduce thermal fatigue in a junction portion of an external wiring to enhance long-term reliability, where the semiconductor device includes a semiconductor substrate, a transistor portion and a diode portion that are alternately arranged along a first direction parallel to a front surface of the semiconductor substrate inside the semiconductor substrate, a surface electrode that is provided above the transistor portion and the diode portion and that is electrically connected to the transistor portion and the diode portion, an external wiring that is joined to the surface electrode and that has a contact width with the surface electrode in the first direction, the contact width being larger than at least one of a width of the transistor portion in the first direction and a width of the diode portion in the first direction.

Semiconductor device and method of manufacturing semiconductor device

Semiconductor module

A semiconductor device, including a plurality of semiconductor modules, each including a semiconductor element, a main terminal and a wiring portion that connects the semiconductor element and the main terminal, and at least one busbar that each includes a terminal portion, and a plurality of attachment portions, the attachment portions being respectively connected to the main terminals of the semiconductor modules, such that the at least one busbar connects the semiconductor modules in parallel. The largest resistance among all resistances between the terminal portion and each of the attachment portions in each busbar is 10% or less of a resistance of the wiring portion in each semiconductor module. The largest inductance among all inductances between the terminal portion and each of the attachment portions in each busbar is 10% or less of an inductance of the wiring portion in each semiconductor module.

Semiconductor device and busbar

A semiconductor device can include an insulating substrate on which at least four semiconductor elements forming a three-level power conversion circuit are mounted, a base plate on which the insulating substrate is provided, a positive conductor plate with a positive DC potential which is connected to one semiconductor element among the semiconductor elements; a negative conductor plate with a negative DC potential which is connected to another semiconductor element among the semiconductor elements and an intermediate potential conductor plate with an intermediate potential which is connected to the remaining two semiconductor elements among the semiconductor elements. The positive conductor plate, the negative conductor plate, and the intermediate potential conductor plate are provided on the base plate. The positive conductor plate and the negative conductor plate are arranged close to the intermediate potential conductor plate so as to face the intermediate potential conductor plate.

Semiconductor device including positive, negative and intermediate potential conductor plates

A semiconductor device, according to one possible configuration, includes switching circuits, each switching circuit comprising IGBT chips connected in series and clamping diodes. The semiconductor device also includes a first and a second wiring line and auxiliary emitter lines. The first wiring line and a first auxiliary emitter line connect the emitter terminals of IGBT chips of the first and second switching circuits. The second wiring line and another auxiliary emitter line connect the emitter terminals of the third IGBT chips of the first and second switching circuits. The wiring lines have a large current carrying capacity and a lower resistance value than their respectively connected auxiliary emitter line.

In some aspects of the invention, multiple insulating substrates each mounting thereon at least one each of at least four semiconductor devices that form at least one of three-level electric power inverter circuits and a base plate on the one surface of which a plurality of the insulating plates are arranged are provided. On the one surface of the base plate, at least four regions are established and multiple insulating substrates are arranged to be distributed so that at least one each of the at least four semiconductor devices is arranged in each of the four regions established on the base plate. This can make the semiconductor devices arranged to be distributed so that heat generating sections determined according to the operation mode of the semiconductor system comes to be partial to disperse generated heat, by which a semiconductor system is provided which can enhance heat dispersion efficiency.

Semiconductor system with at least one three-level electric power inverter circuit

In order to enable detection of degradation of the heat dissipation from a semiconductor chip, even when the operating state of a semiconductor device cannot be predicted, a thermal resistance calculation circuit calculates the thermal resistance of the heat dissipation path from the semiconductor chip, based on the loss of a switching element calculated by a loss calculation circuit and the temperature of the semiconductor chip calculated by a temperature calculation portion, and when the voltage corresponding to the thermal resistance calculated by the thermal resistance calculation circuit exceeds a reference voltage, switching operation of the switching element is halted.

An abnormality detection and protection circuit is provided in association with a driving circuit for a semiconductor device, for detecting plural types of abnormalities and protecting the device from the abnormalities. The present circuit includes a plurality of abnormality detecting devices for detecting the plural types of abnormalities, respectively, a plurality of abnormality storage circuits each provided for the corresponding abnormality detecting devices for storing occurrence of the corresponding type of abnormality, and an abnormality transmitting circuit that transmits a signal representing the detected type of the abnormality to an overall control system for controlling a plurality of semiconductor devices. The circuit of the invention further includes an operation stopping device for stopping a switching operation of the semiconductor device, which device is immediately operated if the detected abnormality is of a type that requires emergency protection, so as to automatically stop the switching operation of the semiconductor device.

Growing community of inventors

Azumino, Japan

Hiroaki Ichikawa