Matsushita Electric Industrial Co., Ltd.

Kyocera Corporation

Nec Corporation

Hiroaki Hirata

Kozo Kimura

Akio Nishimura

Kenichiro Sumida

Takashi Hirano

Mitsuo Yamashita

Noriyasu Kawakita

Tatsuji Kanbara

Hiroshi Ueda

Takeshi Kyouda

Ryota Teshima

Kiyoshi Shibayama

Atsushi Nunome

Hideaki Fukui

Akihito Ito

Ken-ichiro Sumida

Kyouichi Ibaraki

Ken-Ichiro Sumida

Tatsuji Kambara

The solar cell module comprises: a string including solar cell elements, each including a first main surface being rectangular in shape and an electrode extending along a longitudinal direction on the first main surface, and an interconnection connecting the solar cell elements adjacent to each other along the longitudinal direction; a light-transmitting member located to cover the string; and a sealing material located between the string and the light-transmitting member. Each of solar cell elements includes a silicon substrate with the first and second main surface, and a first and second side surfaces each connecting the first and second main surface, the second side surface being located on the back side of the first side surface. The first and second side surfaces are arranged along the longitudinal direction, where silicon is exposed on the first side surface and the second side surface is covered with an insulating layer.

Solar cell module and method of manufacturing solar cell module

A solar cell module is disclosed. The solar cell module includes a solar cell panel, first and second holding members, a reinforcing member. The panel includes a light-receiving surface, a non-light receiving surface, a first side part and a second side part. The first and second holding members hold the first and second side parts respectively. The reinforcing member is laid across the first and second holding member on a non-light receiving surface side. The adhesive is disposed between the non-light receiving surface and the reinforcing member. The reinforcing member includes a supporting part that is disposed with a gap with the non-light receiving surface and that supports the non-light receiving surface via the adhesive. The supporting part includes a first main surface, a second main surface and a through hole. At least one part of the adhesive is located within the through hole.

Solar cell module

A photovoltaic power generating system of the present invention includes a solar cell module, an installation platformfor holding a pair of ends of the solar cell module, and at least one supporting memberdisposed on a side of a non-light-receiving surfaceB of the solar cell module, wherein the supporting memberis disposed at such a distance from the non-light-receiving surfaceB of the solar cell modulethat the supporting membercan abut against the non-light-receiving surfaceB by deformation of the solar cell moduleA deforming amount of the solar cell moduleis increased in accordance with an external force applied to the solar cell module

Photovoltaic power generating system

A DHCP serverdispenses an IP address in response to a request from a terminal equipment. An authentication serverreceives an authentication frame transmitted from the terminal equipmentusing the dispensed IP address as a sender address and authenticates the terminal equipment. Upon completion of authentication, the authentication serverinforms a registration information databaseof an authentication hubof communication permission for the terminal equipment. In the authentication hub, a frame receiving circuitreceives a transmission frame transmitted from the terminal equipment. The authentication hubrefers to the registration information databaseon the basis of sender information of the transmission frame, determines transmission, rewriting-and-transmission, or discarding for the frame, and sends the transmission frame to a transmission bufferif transmission or rewriting-and-transmission is permitted for the frame.

Authentication system, network line concentrator, authentication method and authentication program

Disclosed is an information processor comprising multiple instruction setup units which fetch and decode instructions as the first half of the procedure in instruction pipelines, each of the instruction setup units being in charge of processing instruction streams. The decoded results are scheduled in instruction schedule units and sent to each corresponding function unit to be executed.

Apparatus for simultaneously scheduling instructions from plural

The present invention discloses a multistream instruction processor issuing instructions from N instruction streams in parallel, and processing instruction streams interchangeably when the number of the instruction streams is N or larger than N. Such processor comprises aninstructionpreparationunit comprised of N thread slots each of which fetches/decodes instructions from the instruction stream assigned thereto as well as issues decoding result one at a time; a functional unit comprised of M instruction execution units each of which executes instructions in accordance with the decoding result of the thread slot; an execution connection unit for replacing a connection with another, the connection between the instruction preparation unit and the functional unit so that the result received from the thread slot will be provided to the execution unit which is ready to execute it; and an instruction stream controller comprised of a context backup memory and an exchange controller, the context backup memory holding a context of the instruction stream which indicates how far execution of the instruction stream had been conducted so that the instruction stream will be re-executed while the exchange controller extracting the context of the instruction stream and temporarily storing it into the context backup memory when a predetermined event happens in the instruction therefrom as well as making the instruction execution unit receive another instruction, the instruction execution unit which was executing the instruction including the predetermined event.

Multistream instruction processor able to reduce interlocks by having a

A cache controller for a multithreading multiprocessor system which starts an execution of another thread by suspending an ongoing execution of a thread when a cache miss happens. The cache controller comprises a cache directory unit for storing cache managing data including a footprint bit to indicate a mapping relation between at least one cache block in a main memory block, an access control unit for searching the directory unit based on an access requesting message inputted thereto through its input/output port connected to a processor to return one of a cache hit notice and a cache miss notice, as well as transferring messages with the main memory through its input/output port connected to a network, and a footprint bit changing device for setting the footprint bit in the cache managing data corresponding to a cache block at a cache hit, while resetting the footprint bit upon input of a positive responding message through the input/output port connected to the network to a fetch requesting message which has been sent therethrough at a cache miss.

Cache block replacement scheme based on directory control bit set/reset

Apparatus for simultaneously scheduling instruction from plural

Growing community of inventors

Kyoto, Japan

Hiroaki Hirata