Hitachi, Ltd.

Hitachi Ulsi Engineering Corp.

Hitachi Microcomputer System, Ltd.

Hiroaki Fujii

Yasuhiro Inagami

Naonobu Sukegawa

Hideya Akashi

Yoshiko Yasuda

Toshiaki Tarui

Shigeo Takeuchi

Yoshio Miki

Katsumi Takeda

Hideo Wada

Tatsuya Kawashimo

Masaru Takeuchi

Akihiro Takamura

Kazuya Hisaki

Tshiaki Tarui

Yoshifumi Takamoto

Kinji Mori

Teruo Tanaka

Naoki Hamanaka

Hitoshi Kakuta

Yasuo Suzuki

Kiyohiro Obara

Katsuyoshi Kitai

Tatsuo Higuchi

Tomohiro Nakamura

Tadaaki Isobe

Masahiro Yamada

Masashi Egi

Yoshiko Tamaki

Ken Naono

Junji Nakagoshi

Yasutsugu Morimoto

Atsuko Koizumi

Toshihiro Eguchi

Taturu Toba

Shinichi Shutoh

Shunji Takubo

Chiaki Kato

Tsunao Kanzaki

Yasuhiro Inagaki

Makoto Koga

Collectively predicting input operations for plural operation object items (subwindows) belonging to a same window. A proposal window PG stores in a statistics information database and manages information about the input entity and an operation object of an input operation accepted from a user, and a window to which the operation object belongs, along with transition information indicating the transition of active windows concerned in previous input operations. When an active window transitions because of an input operation accepted from the user, it searches the statistics information database for information that contains information about a new active window and is associated with transition information matching the transition of active windows concerned in previous input operations.

Device and method for assisting input operations

Reliability is evaluated in constructing a component based-on application and an application for realizing reliability required can be constructed efficiently. A run-time history such as an occurrence frequency of errors, a recovery time required at error occurrence, and a processing capacity at preventive maintenance is added per software component to a run-time history list having been recoded per execution environment such as an application ID, combined component IDs, and executed hardware ID. From these pieces of information, an interval of performing preventive maintenance recommended per software component during system construction is calculated. By comparing reliability per software component and reliability required for the system, advisability is determined and conformance is evaluated. An execution schedule for preventive maintenance and a processing capability are calculated about the entire component-based application created by combining the software components. By calculating the reliability and the processing capability in the entire system to be compared to those required for the entire system, advisability is determined and conformance is evaluated.

Component-based application constructing method

To display many objects within a limited display region so a user can easily select the desired object, the invention includes: processing of arranging the objects in a virtual plane, processing of arranging a projection surface (a virtual projection body) on the virtual plane, processing of computing positions of the objects on the projection surface corresponding to the positions of the objects on the virtual plane, processing of converting the positions on the projection surface into positions on display regions of a display device, processing of displaying the objects on the display regions, and processing of operating the objects on the display regions based on instructions from a pointing device.

Program, method and apparatus for operating objects displayed on a display

A hierarchical server system efficiently balances the processing load thereon and for shortening the processing time therein is provided, such as a web server system. A system controller, a load balancing device, and a shared memory are provided in a multi-layer server system made of a plurality of servers. When processing implemented with a first layer server is temporarily stopped in order to acquire information needed for processing from a second layer server, process information needed to resume the processing is recorded in the shared memory. When the necessary information is sent back to the first layer server, the system controller inquires about work statuses of all first layer servers to select another first layer server to resume the processing based upon the inquiry results. The then selected first layer server then resumes the processing using the information that was sent back and the process information in the shared memory.

Hierarchical server system

A main logical unit and a standby logical unit are defined by a process controller in a shared main memory multiprocessor, and an information storage space accessible from both logical units is provided. The main logical unit stores address information onto that information storage space by indicating a memory area it controls as the main memory area. When failover or cloning becomes necessary, the standby logical unit searches the information on the applicable address. Then from the applicable information, it also searches information on the main memory area controlled by the main logical unit to establish in itself and forms a processing environment and state identical to the main logical unit such that the standby logical unit takes over all or a portion of the processing of the main logical unit. This enables the construction of a server system of high operability to overcome failures and poor response times by failover and cloning, etc.

Server system operation control method

A computer system including a plurality of element processors, and an interconnecting network for connecting the element processors. Each element processor includes a processor, a memory, and a network interface circuit for exchanging messages with the interconnecting network. Each element processor is provided with a message passing library for communicating with user processes running therein and a direct inter-memory data transfer library for communicating with the message passing library and controlling the network interface circuit. The network interface circuit includes a memory read circuit connected to the memory, and a message assembly circuit connected to to memory read circuit for generating a message to be transferred to a destination element processor through said interconnecting network. The memory read circuit reads user data to be transferred and additional information which is to be used in the destination element processor to identify whether the user data is requested by a user process running in said destination element processor based on first and second pieces of address information. The message assembly circuit generates a message which includes a header and send data which includes the user data and the additional information.

Data transfer method for reduced number of messages by message passing library and direct intermemory data transfer library and computer system suitable therefor

A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.

Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas

An instruction processor is employed which performs a cache coherence control according to a request from the storage controller. The storage controller is provided with a cache coherence control processing circuit, which performs the cache coherence control for the addresses which are the destinations of main memory accesses occurring with a data transfer. At the same time, the cache coherence control processing circuit performs the cache coherence control processing once for each cache line in the process of data transfer. The cache coherence control processing performed by software in connection with data transfer is obviated, improving the data transfer efficiency including the cache memory control and reducing limitations on program.

Message passing distributed shared memory system that eliminates

A data processor includes a register group having registers of the number larger than the number of registers which can be designated by a register specifier field of an instruction. The register group consists of a plurality of register queues with respect to logical register numbers designated in the instruction, each register queue including a plurality of physical registers. In the data processor, a physical register number forming section is provided for converting the logical register number to a physical register number in the register queue corresponding to the logical register number, by using queue control information designated in the register specifier field and read/write information decided by the kind of the instruction and the position of the register specifier field in the instruction.

Data processor with multiple register queues

To increase the capacity of usable memory of a parallel processing computer system as a whole and effectively utilize the address space without waste, a variable-length Global/Local allocation field is provided in a fixed-length address. When the field is locally set, the address is used as an address of a local memory area to which the local processor refers. When the allocation is globally set, the remaining address is a variable length logical processor number (this number is converted into a physical processor number) and a variable length offset address, for specifying a global memory area belonging to a processor out of the global areas of memories of a group of some of the processors, which global memory can be referred to by all the processors of the groups. A memory access interface executes memory access to the local or global area of the memory of the local processor or to the global area of the memory of another processor.

Memory access mechanism for a parallel processing computer system with

Parallel processor system including a cache memory subsystem that has

Parallel processors communicate with each other over a network by transmitting messages that include destination processor information. A message controller for each processor in the network receives the messages and checks for faults in the message, particularly in the destination processor number contained in a first word of the message. If a fault occurs in the destination processor number, then the faulty message is transmitted to an appropriate processor for handling the fault. In this way the network operation is not suspended because of the fault and the message is not left in the network as a result of the error occurring in the destination processor number. The processor to which the faulty message is directed is determined by a substitute destination processor number contained in the message or is predetermined and set in another way, such as by a service processor. To recover from the fault, the processor receiving the faulty message can request that the message be retransmitted or the error can be corrected using an ECC, for example. If the faulty message cannot be retransmitted, then the processor or the host processor can request that the job to which the faulty message pertains be canceled by all of the processors executing that job without affecting the simultaneous execution of other jobs by the same processors.

Fault handling and recovery for system having plural processors

A disk apparatus including a disk controller connected to a plurality of drives, each having a plurality of memory disks, and an access method to the disk apparatus, are described. Accordingly, a plurality of drives are grouped into a plurality of drive groups, and a data set is divided into a plurality of partial data having a data quantity that is accessible at a given time by each of the drive groups when an access request is generated from an external apparatus to the disk apparatus. Partial data are written into the different drive groups at different times, and successive partial data are written into different drive groups. The plurality of partial data may be transferred to the drive groups in parallel with the writing of partial data into the memory disks.

Disk array apparatus and method for dividing and reading/writing partial

A data processing unit which can access a greater number of registers than registers addressable by an instruction to realize high-speed execution of a program. To this end, the data processing unit includes a greater number of floating point registers than the number of registers addressable by an ordinary instruction, a window start pointer register, a window start pointer valid register, a conversion circuit, when the window start pointer valid register has a value of 1, for converting a floating point register number in the instruction to a physical floating point register number and for changing a conversion pattern depending on the value of the window start pointer register, a window start pointer set instruction for setting a value at the window start pointer register, and floating point register pre-load and post-store instructions having a register field different in length from the ordinary instruction, and wherein the floating point register number specified by the register field is converted by the conversion circuit to the physical floating point register number on the basis of the value of the window start pointer register.

Data processing unit

A main memory shared by plural processing units in a parallel computer system is composed of plural partial main memories. A directory for each data line of the main memory is generated after the data line has been cached in one of the processing units. The directory is held in one of the partial main memories in place of the data line. The directory indicates a processing unit which has cached the data line. A status bit C provided for the data line is set. If a subsequent read request is given to the data line, the status C bit is checked and the directory is used to identify a processing unit that has cached the data line. The request is transferred to the identified processing unit, and the data line is transferred from that processing unit to the processing unit that has issued the request. If a processing unit that has cached the data line has replaced the data line, it is checked if there is a processing unit that has cached the data line. If there is none, the data line is written back into the one partial main memory. If there is, the data line is not written back. Another status bit RO is also used for each data line. It indicates if the data line is read only. If a data line is read only, generation of the directory and storing it in the partial main memory is prohibited.

Access control method for a shared main memory in a multiprocessor based

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Hadano, Japan

Hiroaki Fujii