Imec Vzw

Hiroaki Arimura

Hendrik F W Dekkers

Antony Premkumar Peter

Jacopo Franco

Benjamin Kaczer

A p-channel metal-oxide-semiconductor (pMOS) transistor including a gate stack which includes: a silicon oxide comprising dielectric interlayer on a substrate, wherein the dielectric interlayer has a thickness below 1 nm; a high-k dielectric layer having a higher dielectric constant compared to the dielectric interlayer; a first dipole-forming capping layer between the dielectric interlayer and the high-k dielectric layer and in direct contact with the dielectric interlayer, for shifting down a high-K bandgap of the high-k dielectric layer with relation to a valence band of the substrate, where the first dipole-forming capping layer has a thickness below 2 nm; at least one work function metal above the high-k dielectric layer. Advantageously, the pMOS transistor includes low negative bias temperature instability (NBTI) and therefore high reliability without the use of a reliability anneal which makes the pMOS transistor suitable for use as back end of line (BEOL) devices.

PMOS transistor including low thermal-budget gate stack

A method for forming a gate stack of a field-effect transistor includes depositing a Si capping layer on a Ge channel material (). The method further includes depositing an oxide layer on the Si capping layer by a plasma enhanced deposition technique at a temperature less than or equal to 200&#xb0; C., and a plasma power less than or equal to 100 W.

Si-passivated GE gate stack

The disclosed technology generally relates to semiconductor devices, and more particularly to transistors comprising germanium (Ge) in the channel, and to methods of manufacturing thereof. In one aspect, a field-effect transistor (FET) comprises an active region comprising germanium (Ge) and a gate stack formed on the active region. The gate stack comprises a Si-comprising passivation layer formed on the active region, an interfacial dielectric layer comprising SiO(x&#x3e;0) formed on the passivation layer, a dielectric capping layer comprising an interface dipole-forming material formed on the interfacial dielectric layer, a high-k dielectric layer formed on the dielectric capping layer and a gate electrode layer formed on the high-k dielectric layer.

Growing community of inventors

Leuven, Belgium

Hiroaki Arimura