Hitachi, Ltd.

Hitachi Engineering Co., Ltd.

Hitachi Microsoftware Systems, Inc.

Hitzchi, Ltd.

Hiroaki Aotsu

Koichi Kimura

Toshihiko Ogura

Tadashi Kuwabara

Hiromichi Enomoto

Tadashi Kyoda

Mitsuru Ikegami

Kiichiro Urabe

Akira Isono

Koichi Okazawa

Nobukazu Kondo

Yasuo Kurosu

Takashi Maruyama

Kazunari Suzuki

Naoya Ikeda

Keiichi Nakane

Satoshi Yoshizawa

Hidefumi Masuzaki

Tetsuya Mochida

Ryoichi Kurihara

Naomichi Nonaka

Hiroyuki Koreeda

Hitoshi Kawaguchi

Kazushi Kobayashi

Seiji Kashioka

Masakazu Ejiri

Yoshihiro Uchiyama

Yoshihiro Yokoyama

Takao Ohsawa

Shigeru Yabuuchi

Akihisa Kaihara

Masaki Kawase

Masuo Goto

Noriyoshi Ogura

Yujiro Tatsuno

Masami Jikihara

Mamoru Fukushima

Yasushi Momochi

Satoshi Kitamura

Takaaki Kai

Keiichi Isamu

Michikazu Isono

Shoji Matsui

Toshiyuki Edakawa

Toshio Shibata

Sadao Nakatsuka

Mitsuji Suzuki

Yoshio Kakihi

Chihiro Tsuchiya

Tetuya Fukunaga

Hirosi Okada

Tsutomu Inayama

Kazuaki Yamamoto

Hiroyasu Sato

Tadashi Kawabara

Yuuichi Makaya

A memory device which includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data, and a controller having a first data input connected to receive first data, a second data input connected to receive second data, a third data input connected to receive a function mode signal, and operation unit for executing operations between the first data and the second data. The operation unit includes a function setting unit for setting a function indicated by a function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the set function is executed for the first and second data. The operation result is written into the selected part of the storage locations during one memory cycle.

Memory device

A bit operation processor having a first address operation unit for updating the address of data in units of byte or multipled bytes for performing operation in units of byte or multiple of bytes, a second address operation unit for updating the address of data in units of bit or multiple of bits, an address control means operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit, and means for fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.

Method and apparatus for bit operational process

Apparatus for bit operational process

A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

One chip semiconductor integrated circuit device having two modes of data write operation and bits setting operation

One chip semiconductor integrated circuit device having two modes of

Memory circuit

A graphic system which includes a display device having a graphic display area which includes a plurality of display portions and a plurality of one-chip semiconductor integrated circuit devices. Each one-chip semiconductor integrated circuit includes memory for storing a plurality of pixel data, each pixel data includes a plurality of bits and color data, and a logic circuit for carrying out logic operation on a unit of one pixel data read out from the memory based on a function signal supplied to the one-chip semiconductor integrated circuit device. The function signal indicates a relation between the unit of one pixel data read out from the memory and pixel data output by the logic circuit. The invention further includes an external device for supplying the function signal to the one-chip semiconductor integrated circuit device. The logic circuits, of the plurality of one-chip semiconductor integrated circuit devices, each carry out the same logic operation in accordance with the function signal. Further the logic circuit of the one-chip semiconductor integrated circuit device outputs pixel data based on the logic operation carried out by the logic circuit so as to display the pixel data from the logic circuit on one of the display portions of the graphic display area of the display device.

Graphic system including a plurality of one chip semiconductor

A device for displaying pixel data on a graphic display area of a display device. The graphic display area includes a plurality of display portions. The invention includes a memory for storing a plurality of pixel data, each pixel data includes a plurality of bits and color data, and a logic circuit for carrying out a logic operation on a combination of a unit of one pixel data read out from the memory and external data supplied to the device. The logic circuit outputs pixel data based on the logic operation so as to display the pixel data on one of the display portions of the graphic display area of the display device.

One chip semiconductor integrated circuit device for displaying pixel

A memory circuit including memory elements on which the data read, write, and store operations can be arbitrarily performed, the memory elements having a dyadic/arithmetic operation function. utilizing presetting in a read/modify/write mode to be executed during a memory cycle and in an interval in which data from the memory elements and data from external devices exist, an operation is executed between the external data and the data in the memory elements and the operation result is stored during a write cycle, thereby achieving a higher-speed operation.

RAM control method and apparatus for presetting RAM access modes

In a memory circuit having a memory device operative to read, write and hold data and an operation unit implementing computation between a first datum supplied externally and a second datum read out of the memory device, a selector for selecting one of operational function specification data preset externally and a selector for selecting one of bit write control data present externally are given with select control signals, so that a frame buffer memory operative in read-modify-write mode can be used commonly.

Memory circuit and method for setting an operation mode

Growing community of inventors

Yokohama, Japan

Hiroaki Aotsu