Sony Corporation

Hiroaki Anmo

Hiroyuki Miwa

Takayuki Gomi

Takashi Noguchi

Hirokazu Ejiri

Shigeru Kanematsu

Katsuyuki Kato

Norikazu Ouchi

Minoru Nakamura

Koji Kobayashi

Masashi Takeda

Takayuki Mogi

Akio Kayanuma

Norikazu Chuchi

Shigeru Moriuchi

A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

Manufacturing method for making bipolar device having double polysilicon

A BiCMOS semiconductor device comprising a substrate, a vertical bipolar transistor provided on the substrate and having a first conductive base terminal electrode formed in a portion of a first semiconductor film provided on the substrate, a second conductive semiconductor terminal electrode formed in a second semiconductor film provided through an insulating layer on the first semiconductor film, the first and second conductive electrodes being disposed such that portions thereof overlap each other, and an LDD (lightly doped drain)-type MOS transistor provided on the substrate and having a gate electrode formed in a portion of said first semiconductor film and a gate side wall formed on a side wall of said gate electrode, wherein the insulating layer is caused to exist selectively in a region in which the first and second conductive electrodes are overlapped, and constitutes at least a portion of the gate side wall.

Method of making BiCMOS semiconductor device

Manufacturing method for making bipolar device

A method for producing a semiconductor device which decrease the number of processes at the time of producing BiCMOSLSI than the usual. Impurities are introduced into a semiconductor substrate under a second insulating film and a first electric conductive film utilizing a first insulating film and the first conductive film formed on the semiconductor substrate as masks. Therefore, it is able to perform concurrent introduction of impurities into the gate electrode, the source and the drain of the MOSFET, the base electrode of the bipolar transistor, the emitter and the collector contact of the lateral bipolar transistor, the outlet electrode of the capacitor, and the resistor, so that the number of process steps can be reduced.

Method for producing a Bi-MOS device

Method for making bipolar transistor having double polysilicon structure

A bipolar transistor including a semiconductor layer formed on a semiconductor substrate; a base region formed at an upper portion of the semiconductor layer; a graft base region formed at the upper portion of the semiconductor layer so as to connect with a periphery of the base region; an emitter region formed at an upper portion of the base region; an offset insulating film formed on the base region around the emitter region; a collector buried region formed in the semiconductor layer below the base region; a collector drawn region formed in the semiconductor layer so as to connect with the collector buried region and be arranged on the side of the base region adjacent to an element isolating region; an emitter electrode formed on the offset insulating film so as to connect with the emitter region; an emitter insulating film formed so as to cover the emitter electrode; a base electrode formed so as to connect with the graft base region and contact with the emitter insulating film; and a collector electrode formed so as to connect with the collector drawn region.

Manufacturing method for bipolar transistor

A semiconductor device comprises a semiconductor substrate provided with a collector region a base region and an emitter region in a lateral arrangement. Respective portions having peak impurity concentrations of the collector region and the emitter region are formed within the semiconductor substrate. A method of fabricating a semiconductor device comprises a step of forming a collector region of a second conduction type and an emitter region of a second conduction type in a lateral arrangement in a semiconductor substrate serving as a base region of a first conduction type by using a first mask provided with a pair of openings, and a step of forming heavily doped regions of the second conduction type so as to be connected respectively to the collector region and the emitter region by using a second mask provided with a pair of openings separated from each other by a distance greater than the distance between the openings of the first mask.

Semiconductor device having enhanced impurity concentration profile

In a semiconductor integrated circuit device of master slice approach according to this invention, regions on basic elements which are not used and isolation areas serve as wiring regions. Resistive elements are formed on the regions on the basic elements which are not used and the isolation areas. A high integration level can be obtained, circuit layout can be facilitated, and versatility of circuit design can be improved.

Semiconductor integrated circuit device of master slice approach

A semiconductor device with a capacitive element of an MIS structure comprising an electrode lead segment and an MIS segment in which an electrode is formed through a dielectric layer on an impurity region over to an aperture in a field insulator film. A high-concentration impurity region which connects the impurity region of the MIS segment to the electrode lead region of the electrode lead segment is formed only in the junction between the impurity region and the electrode lead region. The parasitic capacitance between the capacitive element and the semiconductor substrate is reduced without increasing the parasitic resistance so as to consequently achieve high precision in forming the capacitive element.

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Kanagawa, Japan

Hiroaki Anmo