Nec Corporation

Hiroaki Anada

Toshihiko Okamura

A parallel decoder, which is simpler and more flexible than conventional devices, is provided in decoding device for a LDPC code. The present invention includes a plurality of memory units for storing a received value and a message generated during a Message-Passing decoding, a plurality of variable node function units, a plurality of check node function units, a plurality of address generation units for generating an address of each of memory units, and a plurality of shuffle network units for determining a connection between variable node function units and check node function units. An address generation unit generates an address on the basis of a plurality of permutations. Each shuffle network unit is connected to some of the variable node function units. This connection is determined on the basis of a plurality of permutations. A change of the permutations in the address generation units and a change of the permutations in the shuffle network units are performed in the same cycle in a decoding process.

Device, program, and method for decoding LDPC codes

In an error correction code decoding apparatus, utilized in the decoding of turbo codes, plural number of backward processing modulesandare provided. In one backward processing module, received data and a priori information are periodically read in the reverse order from memoriesandto calculate backward values. The other backward processing modules are supplied with received data and the a priori information, output from the preset other backward processing module to calculate backward values. The backward processing module reading in from the memories is cyclically changed. A forward processing and soft-output generating modulegenerates a soft-output by exploiting the backward values calculated by the backward processing module which lies directly ahead of the backward processing module reading in the data from the memories.

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Tokyo, Japan

Hiroaki Anada