Hitachi, Ltd.

Hiraku Nakano

Hiroshi Murayama

Hozumi Hamada

A rational number operation unit comprising division means which receives a rational number having numerator and denominator to be reduced for sequentially determining terms d.sub.1, d.sub.2, . . . of a continued fraction for the rational number ##STR1## or data S.sub.1, S.sub.2, . . . , the division means carrying out a first division for the numerator as a dividend and the denominator as a divisor, producing a quotient thereof as the first term d.sub.1 or the dependent data S.sub.1, carrying out a second division for a residue thereof as a new divisor and the divisor in the first division as a new dividend, producing a quotient thereof as the second term d.sub.2 or depending data S.sub.2, . . . , carrying out an (i+1)th division for a residue of the i-th division as a new divisor and the divisor in the i-th division as a new dividend, producing a quotient thereof as the term d.sub.i+1 or depending data S.sub.i+1, calculation means responsive to the term d.sub.i or depending data S.sub.i for calculating

Rational number operation unit for reduction

High and low order bit carry propagation adders are connected to outputs of carry save adder trees which produce half-sums and half-carries. Following carry propagation addition of the low order bits carry propagation addition of the high order bits is carried out. A carry from the low order bit carry propagation addition is added to the high order bit carry propagation addtion.

Vector multiplier having parallel carry save adder trees

In a vector divide apparatus having one or few multipliers, a division between two vectors each comprising a plurality of vector elements is performed. A predetermined number of partial quotients are repetitively calculated for each division between vector elements by using the multiplier. In order not to overlap the division operation between consecutive vector elements during calculation of partial quotients using the multiplier, the period of starting the division between vector elements is shortened whereby the vector divide apparatus can be pipelined.

Pipelined vector divide apparatus

A divide method and a divide apparatus for use in a data processing system. The divisor and dividend are normalized in a normalization circuit. A table unit stores a plurality of approximate reciprocal divisors and differences between adjacent approximate reciprocal divisors and is addressed by the high-order bits of the normalized divisor. The approximate reciprocal divisor read out from the table unit is, in an interpolation approximation circuit, changed into an interpolation approximated approximate reciprocal divisor in accordance with a plurality of bits following the high-order bits and the difference. A multiplication unit multiplies the interpolation approximated approximate reciprocal divisor by the normalized dividend to output a quotient.

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Hadano, Japan

Hiraku Nakano