Renesas Electronics Corporation

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Other

Hiraku Chakihara

Yasushi Ishii

Akio Nishida

Mitsuhiro Noguchi

Hiroyuki Uchiyama

Yoshiyuki Kawashima

Kousuke Okuyama

Masahiro Moniwa

Teruhisa Ichise

Michimoto Kaminaga

Kentaro Saito

Kota Funayama

Koichi Toba

Makoto Mizuno

Keiji Okamoto

Tadanori Yoshida

Yasuhiko Takahshi

Masahiro Tadokoro

Yasuhiko Takahashi

Naonori Wada

Takashi Hashimoto

Tomohiro Hayashi

Tsutomu Okazaki

Takuro Homma

Hideki Sugiyama

Hiroshi Nishikizawa

Toshiyuki Mine

Hideyuki Matsuoka

Naoki Yamamoto

Takahiro Maruyama

Satoshi Abe

Kazuhito Ichinose

Koji Ogata

Akihiro Nakae

Akira Fujimoto

Kyoko Umeda

There is provided a semiconductor device including a first gate pattern on a semiconductor substrate, a second gate pattern adjacent to a side surface of the first gate pattern via an ONO film, and an active region located just below the second gate pattern via the ONO film. Here, an element isolation region is formed just below the first gate pattern. In this manner, capacitance between the first gate pattern and the semiconductor substrate and capacitance between the first and second gate patterns are prevented from being measured when measuring capacitance between the second gate pattern which is an upper electrode and the active region which is a lower electrode in order to measure a film thickness of the ONO film just below the second gate pattern.

Semiconductor device and method of manufacturing the same

Improvements are achieved in the characteristics of a nonvolatile memory. In plan view, in a first isolation region which is an element isolation region surrounded by a first fin, a second fin, a memory gate electrode, and another memory gate electrode, a protruding portion is provided. In a second isolation region which is the element isolation region overlapping the memory gate electrode in plan view, a second isolation portion is provided to set the protruding portion higher in level than the second isolation portion. In a step of lowering a top surface of the element isolation region located between the first and second fins, a part of the element isolation region located between the first and second fins is covered with a mask film to form the protruding portion. Using the protruding portion, a short circuit between the memory gate electrodes due to a gate residue is prevented.

Semiconductor device

In a semiconductor device, a memory cell is formed of a control gate electrode and a memory gate electrode adjacent to each other, a gate insulating film formed below the control gate electrode and an insulating film formed below the memory gate electrode and having a charge accumulating part therein. Also, in this semiconductor device, a capacitive element is formed of a lower electrode, an upper electrode and a capacitive insulating film formed between the upper electrode and the lower electrode. A thickness of the lower electrode is smaller than a thickness of the control gate electrode.

Semiconductor device and manufacturing method thereof

After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.

Method of manufacturing a semiconductor device

To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Method of manufacturing semiconductor device

The memory cell includes a gate insulating film, a control gate electrode, a cap insulating film, a cap layer, another gate insulating film, and a memory gate electrode. A laminated capacitive element includes a capacitive electrode which is constituted by a sub-electrode and another sub-electrode formed of mesa portions (protruding portions) disposed on the sub-electrode at a predetermined interval and each having an upper surface and side surfaces, a capacitive insulating film which is formed along an upper surface of the sub-electrode and the upper surface and the side surfaces of the another sub-electrode, and another capacitive electrode which is formed on the capacitive insulating film. Further, the control gate electrode and the sub-electrode are made of a conductor film, the cap layer and the another sub-electrode are made of other conductor film, and the memory gate electrode and the another capacitive electrode are made of another conductor film.

In an MONOS-type memory cell with a split gate structure, short circuit between a selection gate electrode and a memory gate electrode is prevented, and reliability of a semiconductor device is improved. In a MONOS memory having a selection gate electrode and a memory gate electrode that are adjacent to each other and that extend in a first direction, an upper surface of the selection gate electrode in a region except for a shunt portion at an end portion of the selection gate electrode in the first direction is covered with a cap insulating film. The memory gate electrode is terminated on the cap insulating film side with respect to a border between the cap insulating film and an upper surface of the shunt portion exposed from the cap insulating film.

In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film () formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.

A semiconductor device having improved reliability is disclosed. In a semiconductor device according to one embodiment, an element isolation region extending in an X direction has a crossing region that crosses, in plan view, a memory gate electrode extending in a Y direction that intersects with the X direction at right angles. In this case, in the crossing region, a width in the Y direction of one edge side, the one edge side being near to a source region, is larger than a width in the Y direction of the other edge side, the other edge side being near to a control gate electrode.

A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

Semiconductor device and manufacturing method of semiconductor device

The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed.

Method for manufacturing a semiconductor device

The performances of a semiconductor device are improved. The semiconductor device has a first control gate electrode and a second control gate electrode spaced along the gate length direction, a first cap insulation film formed over the first control gate electrode, and a second cap insulation film formed over the second control gate electrode. Further, the semiconductor device has a first memory gate electrode arranged on the side of the first control gate electrode opposite to the second control gate electrode, and a second memory gate electrode arranged on the side of the second control gate electrode opposite to the first control gate electrode. The end at the top surface of the first cap insulation film on the second control gate electrode side is situated closer to the first memory gate electrode side than the side surface of the first control gate electrode on the second control gate electrode side.

Semiconductor device and a manufacturing method thereof

Growing community of inventors

Akishima, Japan

Hiraku Chakihara