Intel Corporation

Hing (Thomas) Yan To

Gregory Lemos

Jun Cai

Matt Dayley

Disparate clock domains are resynchronized after circuits in one of the clock domains awake from a reduced power state. Parallel test data is routed from a core circuit to a parallel-to-serial converter in an input/output (I/O) circuit. The parallel-to-serial converter clocks the parallel test data in response to a load signal. The load signal is varied until the clock domains are synchronized.

Disparate clock domain synchronization

An integrated circuit includes current mode drivers that provide equalized outputs. A parallel-to-serial converter circuit receives data at less than one fourth the output data rate, and provides main data and equalization data at one fourth the output data rate to at least one four-to-one multiplexer. The main data and equalization data is multiplexed onto an output node at the output data rate.

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Cupertino, CA, United States of America

Hing (Thomas) Yan To