Intel Corporation

Himanshu Sinha

Altug Koker

Josh B Mastronarde

Russell W Dyer

David J McDonnell

A method and apparatus for synchronizing a synchronizing clock is disclosed for use in synchronizing a high-speed memory bus with a second, heritage memory bus. This method and apparatus includes generating an initial synchronizing clock from a reference clock of the high-speed memory bus. It then includes receiving a synchronizing packet on the high-speed memory bus utilizing the initial synchronizing clock. Finally, it includes delaying a clock transition of the initial synchronizing clock in response to the received data of the synchronizing packet.

Method and apparatus for remote memory clock synchronization for optimized leadoff performance

An embodiment of a memory controller that improves main memory bandwidth utilization during graphics translational lookaside buffer fetch cycles is disclosed. The memory controller includes a first request path and a second request path. The memory controller further includes a graphics translational lookaside buffer that includes a cache. The graphics translational lookaside buffer issues an address fetch request to a memory interface when a graphics memory request received from the first request path or from the second request path misses the cache. The memory controller also includes a memory arbiter that includes a first request path cycle tracker and a second request path cycle tracker. The memory arbiter allows a request received from the second request path to be issued to the memory interface when a graphics memory request received from the first request path is stalled due to a graphics translational lookaside buffer cache miss.

Method and apparatus for improving system memory bandwidth utilization during graphics translational lookaside buffer cache miss fetch cycles

An apparatus and method for instantly configuring a controller are provided. In one embodiment, a controller is configured by selecting an simultaneous configuration input vector, and placing at least a portion of the configuration input vector in a plurality of registers in the controller during a single clock cycle.

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Citrus Heights, CA, United States of America

Himanshu Sinha