Freescale Semiconductor,inc.

Himanshu Kukreja

Deepak Agrawal

Himanshu Goel

Siddhartha Jain

A circuit for reducing peak power during transition fault testing of an integrated circuit (IC) includes a programmable register that receives scan shift and SDI (scan data in) signals. Input and output ports of the programmable register are connected together. A multiplexer is provided that has a first input port that is maintained asserted, and a second input port connected to the output port of the programmable register. A scan shift signal, which remains asserted during a scan shift operation and de-asserted during a scan capture operation, is provided at a select input port of the multiplexer. The output of the multiplexer is provided as an input to a clock gating cell. The clock gating cell selectively provides the clock signal to the scan-chain flip-flops in the IC based on the scan shift signal and a functional enable signal, and reduces peak power during transition fault testing.

Circuit to reduce peak power during transition fault testing of integrated circuit

An integrated circuit (IC) having a low leakage current mode of operation has a number of modules for running respective applications. The modules have respective cells and respective test scan chain elements. The IC also has a controller for configuring an active module to operate in a functional mode and a selected inactive module to operate in a low leakage current mode. Configuring the selected inactive module to operate in low leakage current mode includes enabling scan mode of the selected inactive module, and applying a low leakage vector of input signals from the controller to the cells of the inactive module using the scan chain. Functional data outputs of the inactive module are disabled during low leakage current mode. In the meantime, the active modules continue to operate in the functional mode.

Low leakage current operation of integrated circuit using scan chain

A system and method for scan partitioning for testing an embedded logic circuit in an integrated circuit (IC) device is provided. One or more scan partitions in the embedded logic circuit are identified. Each scan partition includes one or more scan chains of scan registers. One or more interacting registers connecting scan registers of a first scan partition and scan registers of a second scan partition are identified and combined to form an interacting scan chain. The embedded logic circuit is tested by selectively activating the scan chains of the first and second scan partitions and the interacting scan chain.

Growing community of inventors

New Delhi, India

Himanshu Kukreja