Qualcomm Incorporated

Integrated Device Technology, Inc.

Renesas Electronics America Inc.

Himanshu Khatri

Samet Zihir

Tumay Kanar

Ojas Choksi

Wei Zhuo

Bhushan Shanti Asuri

Vinod Panikkath

Janakiram Ganesh Sankaranarayanan

Hongyan Yan

Eugene Robert Worley

Li Liu

Prasad Srinivasa Siva Gudem

Kevin Hsi-Huai Wang

Faramarz Sabouri

Maulin Pareshbhai Bhagat

Hong-Ming Lee

Devavrata Vasant Godbole

Meng Li

Mark Cuezon

Kevin Sheng

Vinod V Panikkath

Maulin Bhagat

Devavrata V Godbole

Methods and systems for operating a transceiver are described. A transceiver can include an upconverting mixer, a downconverting mixer, a controller, and an envelope detector. The upconverting mixer can mix an input signal with a local oscillator (LO) signal to generate a transmitter signal. The envelope detector can receive the transmitter signal outputted from the upconverting mixer and output an envelope of the transmitter signal to an output line of the downconverting mixer. The envelope can indicate at least one of a leaked LO signal and an image signal. The controller can receive a calibration parameter that is based on at least one of the leaked LO signal and image signal and calibrate the upconverting mixer based on the calibration parameter.

Spurious emissions detection and calibration using envelope detector

An apparatus includes a transmit-receive switch circuit and a detector circuit. The transmit-receive switch circuit may be connected between an input port, an output port, and a common port, and configured to switch a transmit radio-frequency signal from the input port to the common port in a transmit mode and a receive radio-frequency signal from the common port to the output port in a receive mode. The detector circuit may be integrated within the transmit-receive switch and may be configured to generate a power detection signal in response to at least one of the transmit radio-frequency signal or the receive radio-frequency signal.

Transmit-receive switch with integrated power detection

An apparatus comprises an amplifier circuit and a bias circuit. The bias circuit is generally configured to dynamically adjust a bias voltage reference at a bias node connected to one or more input transistors of the amplifier circuit to maintain a low baseband impedance.

Power amplifier bias network implementation for improving linearity for wideband modulated signals

An apparatus includes a log amplifier and a calibration circuit. The log amplifier may be configured to generate an output signal in response to an offset between a first voltage and a second voltage. The calibration circuit may be configured to disconnect an input power and perform a cancellation of the offset when the input power is not present. The first voltage may be generated by the apparatus in response to a power detection. The second voltage may be received from a reference circuit. The cancellation of the offset may extend a working range of the apparatus. The output may provide a linear-in-dB power detection.

Linear-in-dB log-amp with calibration for power detection

An apparatus comprises a plurality of transceiver circuits, a memory, and an interface circuit. The memory generally embodies a table associating a plurality of index values with corresponding gain and phase values for each channel of each of the transceiver circuits. In a first mode, the interface circuit may be configured to receive the corresponding gain and phase values associated with each of the plurality of index values and store the corresponding gain and phase values in the table. In a second mode, the interface circuit, in response to receiving one of the index values, configures each channel of each of the transceiver circuits with the corresponding gain and phase values from the table.

Multi-mode control with fast-access lookup table implementation

An apparatus includes a plurality of impedance matching networks, a common port, a first switch circuit and a second switch circuit. The impedance matching networks may be (i) connected in series between an input port and an output port and (ii) configured to generate a power detection signal in response to a radio-frequency signal. The radio-frequency signal may be a transmit signal or a receive signal. The common port may be (i) connected to the impedance matching networks and (ii) connectable to an antenna. The first switch circuit may be configured to switch the input port and a circuit ground potential. The second switch circuit may be configured to switch the output port and the circuit ground potential.

An apparatus is described. The apparatus includes an input device. The apparatus also includes a positive supply voltage pad. The apparatus further includes an input signal pad. The apparatus also includes a ground pad. The apparatus further includes charged-device model protection circuitry that protects the input device from electrostatic discharge. The charged-device model protection circuitry includes at least one of de-Q circuitry and a cascode device.

Radio frequency integrated circuit (RFIC) charged-device model (CDM) protection

Techniques for improving performance of a transformer shared amongst a plurality of operating modes. In an aspect, first and second primary windings of a transformer are coupled to an AC ground voltage. Primary windings are mutually coupled to a secondary winding of the transformer. To render the second primary winding inactive, e.g., when operating in a first mode, a switch coupling the second primary winding to the common reference voltage is opened. Similarly, when it is desired to render the first primary winding inactive, e.g., when operating in a second mode, a switch coupling the first primary winding to the common reference voltage is opened. In this manner, the inactive primary winding advantageously does not load the secondary winding. Further aspects provide for, e.g., extending the techniques to more than two modes, and alternative techniques to mutually couple the signal from the primary to the secondary winding.

Port isolation in shared transformers

A device includes an adjustable capacitance and a switchable inductance coupled to the adjustable capacitance and configured as a tunable resonant circuit, the switchable inductance comprising a tapped structure having a first inductance and a second inductance.

Tunable radio frequency (RF) front-end architecture using filter having adjustable inductance and capacitance

Bias voltage generators that can generate variable bias voltages for transistors in mixers and other circuits are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit (IC)) includes at least one transistor and a bias voltage generator. The transistor(s) have a threshold voltage and receive a bias voltage. The bias voltage generator generates the bias voltage based on changes to the threshold voltage of the transistor(s), e.g., due to IC process and/or temperature. In an exemplary design, the bias voltage generator includes a replica transistor that tracks the transistor(s) and an op-amp that provides a gate voltage for the replica transistor. The bias voltage is generated based on the gate voltage. The bias voltage generator may generate the bias voltage (i) to track the threshold voltage of the transistor(s) in a first mode or (ii) based on a fixed voltage in a second mode.

Threshold tracking bias voltage for mixers

Exemplary embodiments are directed to providing electrostatic discharge (ESD) protection of a cascode device of an amplifier. In an exemplary embodiment, a transistor is configured to receive a bias voltage and at least one circuit element coupled to the transistor and configured to receive an input voltage via an input pad. Additionally at least one diode can be coupled to a drain of the first transistor and configured to limit a voltage potential at an internal node of the amplifier caused by the input pad.

Electrostatic discharge protection of amplifier cascode devices

Amplifiers with shunt switches to mitigate interference are disclosed. In an exemplary design, an apparatus includes an amplifier and a shunt switch. The amplifier has an input operatively coupled to an input/output (I/O) pad of an integrated circuit (IC) chip. The shunt switch grounds the amplifier when the shunt switch is closed. The shunt switch is isolated from the I/O pad and the amplifier input. The amplifier may be a low noise amplifier (LNA) or some other type of amplifier. In an exemplary design, the shunt switch is isolated from the I/O pad by a series switch. The series switch and the shunt switch may be closed when the amplifier is disabled and may be opened when the amplifier is enabled.

Amplifiers with shunt switches

Disclosed are circuits, techniques and methods for implementing an attenuator in a signal transmission path. In one particular implementation, an attenuation may be adjusted based, at least in part, on a control signal. In another implementation, such an attenuation may be adjusted in coarse increments by varying one or more gate voltages applied one or more transistors. In yet another implementation, adjusting said attenuation in fine increments by varying a bias voltage applied to at least one level shifter.

Programmable attenuator

Techniques for designing a single-balanced mixer coupled to a dummy portion with a dummy load to improve noise rejection. In an aspect, a single-ended signal (RF) from a stage preceding the mixer, e.g., a low-noise amplifier (LNA), is coupled to the input of the single-balanced mixer to be mixed with a local oscillator (LO) signal. A dummy portion replicating the topology of the single-balanced mixer is coupled to the single-balanced mixer to improve noise rejection, with the LO signal also provided to the dummy portion. The input of the dummy portion may be coupled, e.g., to a dummy load, which is designed to replicate the loading characteristics of the preceding stage, e.g., the LNA.

Mixer architectures

In a first aspect, an RF switch includes a main transistor and a gate-to-source shorting circuit. When the RF switch is turned off, the gate-to-source shorting circuit is turned on to short the source and gate of the main transistor together, thereby preventing a Vgs from developing that would cause the main transistor to leak. When the RF switch is turned on, the gate-to-source shorting circuit is turned off to decouple the source from the gate. The gate is supplied with a digital logic high voltage to turn on the main transistor. In a second aspect, an RF switch includes a main transistor that has a bulk terminal. When the RF switch is turned off, the bulk is connected to ground through a high resistance. When the RF switch is turned on, the source and bulk are shorted together thereby reducing the threshold voltage of the main transistor.

Growing community of inventors

San Diego, CA, United States of America

Himanshu Khatri