Tensilica, Inc.

National Semiconductor Corporation

Cadence Design Systems, Inc.

Himanshu A Sanghavi

William A Huffman

Earl A Killian

James Chinmo Kim

Eileen Margaret Peters Long

Darin Stamenov Petkov

Peng Tu

Nupur B Andrews

James Robert Kennedy

Christopher Konrad Wolf

Ygal Arbel

A technique that improves both processor performance and associated data bandwidth through user-defined interfaces that can be added to a configurable and extensible microprocessor core. These interfaces can be used to communicate status or control information and to achieve synchronization between the processor and any external device including other processors. These interfaces can also be used to achieve data transfer at the rate of one data element per interface in every clock cycle. This technique makes it possible to design multiprocessor SOC systems with high-speed data transfer between processors without using the memory subsystem. Such a system and design methodology offers a complete shift from the standard bus-based architecture and allows designers to treat processors more like true computational units, so that designers can more effectively utilize programmable solutions rather than design dedicated hardware. This can have dramatic effects not only in the performance and bandwidth achieved by designs, but also in the time to market and reuse of such designs.

Method and apparatus for providing user-defined interfaces for a configurable processor

A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maintaining the simplicity of programming and allowing efficient physical implementation. Most of the application code can be encoded using two sets of narrow size instructions to achieve high code density. Adding a third (and larger, i.e. VLIW) instruction size allows the architecture to encode multiple operations per instruction for the performance critical section of the code. Further, each operation of the VLIW format instruction can optionally be a SIMD operation that operates upon vector data. A scheme for the optimal utilization (highest achievable performance for the given amount of hardware) of multiply-accumulate (MAC) hardware is also provided.

Vector co-processor for configurable and extensible processor architecture

Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion

A system () for decoding a data stream allocated into data packets contains a control unit (), a stream demultiplexer (), audio and video decoders (and), a memory management unit (), and audio and video input and output buffers. Upon demultiplexing and depacketizing the data packets without interrupting the control unit, the demultiplexer sends encoded audio and video data to the audio and video input buffers. Video messages dealing with video timing information and identifying where encoded video data is stored in the video input buffer are furnished by the demultiplexer for use by the control unit. Utilizing corresponding video instructions provided from the control unit, the video decoder decodes encoded video data to produce decoded video data supplied to the video output buffer. The audio decoder decodes encoded audio data to produce decoded audio data supplied to the audio output buffer. The memory management unit controls transfer of decoded audio data to and from the audio output buffer.

System and method for decoding audio/video data such as DVD or/and DVB data

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Fremont, CA, United States of America

Himanshu A Sanghavi