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Signalchip Innovations Private Limited

Texas Instruments Corporation

Signalchip Innovations Pvt. Ltd.

Himamshu Gopalakrishna Khasnis

Nikhil Birur Gururaja Rao

Anantha Melavarige Subraya

Aravind Ganesan

Naveen Mahadev

Navaneetha Krishnamurthy

Thomas N Zogakis

Srinivasan Venkataraman

Anjana Ghosh

Kandasamy Shanmugam

Baireddy Vijayavardhan

Krishnan Ramabhadran

Amaresh Heggadde Shivananda

Sukrutha Bharadwaj Hebbagilu Krishna

Sujith Kumar Nagaraj

Kishen Amarnath

Mugundhan Varadanarayanan

Sachin Madhukar Dhareshwar

Manoj S Soman

A global navigation satellite system (GNSS) receiver for improving accuracy of a GNSS position estimation using a sigma-delta based fractional interpolation in a delay-locked loop is provided. The GNSS receiver includes a correlator, a code phase discriminator, a first loop filter, a code numerically controlled oscillator, and a sigma-delta modulator. The correlator correlates a GNSS C/A signal received from a satellite with a locally generated GNSS C/A code by multiplying the locally generated GNSS C/A code with incoming data samples. The code phase discriminator determines a delay between the locally generated GNSS C/A code and the GNSS C/A signal received from the satellite. The first loop filter averages the delay measured by the code phase discriminator. The code numerically controlled oscillator generates the local GNSS C/A code based on a unique CA code that corresponds to the satellite. The sigma-delta modulator imparts a fractional delay to the locally generated GNSS C/A code based on an output of the first loop filter.

System and method for global navigation satellite system (GNSS) position estimation

A method for reducing a memory requirement in an uplink receiver using a Sounding Reference Signal (SRS) channel along with a Demodulation Reference Signal (DMRS) for channel estimation in SC-FDMA/OFDM based radio access technologies is provided. The method includes (i) requesting the Sounding Reference Signal (SRS) and receiving the Sounding Reference Signal (SRS), by a base station, from at least one user device and performing corresponding channel estimation, (ii) scheduling, by the base station, at least one of a data or control channel transmission, and (iii) demodulating, using a SC-FDMA/OFDM demodulator, received SC-FDMA/OFDM symbols that corresponds to at least one of the data or control channel transmission scheduled by the base station and saving the demodulated SC-FDMA/OFDM symbols for one DMRS interval in a buffer until channel estimation is ready, thereby reducing the memory requirement of the uplink receiver.

System and method for channel estimation in SC-FDMA/OFDM based radio access technologies

A circuit for detecting, controlling, and maintaining optimal output swing for a noise performance at a given power with an improved operating range is provided. The circuit includes a Voltage Controlled Oscillator (VCO) (), a peak detection circuit () and an Analog Bias Controller (). The VCO includes a bias control that is connected to the output swing of the VCO. The peak detection circuit is added at an output of the VCO. The peak detection circuit detects an output swing of the VCO and controls the output swing by controlling bias of the VCO using a feedback loop. An output voltage of the peak detection circuit is proportional to the output swing of the VCO. The Analog Bias Controller compares the output voltage of the peak detection circuit to a reference (VDD) to maintain the output swing of the VCO at a constant level that corresponds to an internally generated reference.

Peak detection circuit to detect and control output swing level of voltage controlled oscillator

A circuit for matching impedance and regulating a voltage of a high radio frequency line across a low voltage device that includes a differential input port, the high radio frequency lines, an internally routed line, a singled ended peak detection circuit, and a single-ended programmable variable impedance using a single-ended programmable variable impedance. The differential input port receives a differential high radio frequency signal using driver buffers. The internally routed line boosts the received differential high-frequency RF signal. The single-ended peak detection circuit detects peak voltages of the differential high-frequency RF signal. Depending on the peak value obtained at the output of the single-ended peak detection circuit, the single-ended programmable variable impedance that matches the impedance of each of high radio frequency lines and regulates the voltage of high radio frequency lines across said low voltage device to a pre-defined voltage.

Method and circuit for matching impedance and regulating voltage across a low voltage device

A radar system for generating a fast frequency hopping output for frequency agility using a transmitter block and a receiver block. The transmitter block is configured to (i) modulate a digital signal using a first digital mixer, (ii) convert a modulated signal into an inphase analog signal and provide the inphase analog signal to at least one of a first RF IQ mixer or a third RF IQ mixer, (iii) convert the modulated signal into a quadrature analog signal provide the quadrature analog signal to at least one of the first RF IQ mixer or the third RF IQ mixer, and (iv) generate the fast frequency hopping output radar signal by mixing the inphase analog signal and the quadrature analog signal with an inphase RF local oscillator signal and a quadrature RF local oscillator signal.

Pulsed radar system and method with digital mixer for frequency hopping

Disclosed herein is a system and a method for estimating frequency offset of LTE using DMRS and CRC. The system includes one or more modules as follows. A digital filtering and FFT unitperforms FFT operation on a base band signal. An individual user data extraction unitextracts user data individual. A frequency correction unitprocesses the extracted user data if individual. A DEMAP into PUSCH and DMRS unitsplits a corrected frequency signal. An equalizer unitperforms channel equalization. The channel estimation unitdetermines a channel estimation (H). A multiplexer unitreceives the estimated frequency. An equalized data processing and CRC calculating unitreceives and processed the equalized data. A CRC value checking unitdetermines whether a calculated cyclic redundancy check (CRC) value is valid or invalid.

System and method for estimating high speed doppler in LTE using sub-sampling and error indicators

A system for reducing non-linearity in mixed signal processing using complex polynomial vector processoris provided. The complex polynomial vector processorincludes a data processing unit () and a co-efficient feeder unit (). The data processing unit () converts a high-speed data stream into a polar-like format (PL) data and calculates required polynomial powers for the high-speed data stream using the PL format data. The data processing unit () includes a multiplier accumulator (MAC) unit () that generates processed high-speed data and a delay unit () that combines time separated input with the processed high-speed data to generate output data with reduced non-linearity.

System and method for reducing non-linearity in mixed signal processing using complex polynomial vector processor

A single-hop relay cellular systemand a multi-hop relay cellular systemincluding frequency links (A-F), a backhaul link, an access link, and a relay base stationare provided. The relay base stationis configured to interchange a frequency of operation between a first frequency carrierA and a second frequency carrierB for uplink and downlink transmission. Each node in the single-hop relay cellular systemand the multi-hop relay cellular systemis enabled to transmit and receive on frequency carriers through static or dynamic control.

Method and system of relaying in cellular systems

Disclosed herein is a method for automatic gain control based on signal spectrum sensing. Spectral sensing techniques may be employed to detect the presence or absence of interference and also determine a frequency location of the interference and power level estimates of a desired signal. The method includes running an algorithm to measure the energy periodically to track the changes as blockers that were not prominent while experiencing deep fade and those that will affect performance when it is out of the deep fade. The method enables predicting a level of degradation for various front-end settings and enables selection of an optimum setting. In an embodiment, the spectral sensing may be performed either in analog domain using narrowband tunable filters. In an embodiment, the spectral sensing may be performed digitally using Fast fourier transform (FFT), Goertzel algorithm, or power detection techniques.

Automatic gain control based on signal spectrum sensing

A smart antenna system for achieving circularly polarized and electrically down tilted phased array signal is provided. The baseband transmitter transmits a baseband signal. The first voltage controlled oscillator (a) modulates the baseband signal to a plurality of phase shifted intermediate frequency signals, and the second voltage controlled oscillator (b) modulates the plurality of phase shifted intermediate frequency signals to a plurality of phase shifted radio frequency signals. The plurality of power amplifiers amplify the plurality of phase shifted radio frequency signals. The plurality of antennas radiate the plurality of phase shifted radio frequency signals for generating the phased array signals. The phased array signals achieve (i) tilting of an antenna radiation plane of the plurality of antennas from an initial position to a tilted position and (ii) transmitting the plurality of phase shifted radio frequency signals in a circular polarization.

Smart antenna system for achieving circularly polarized and electrically downtilted phased array signals

A method of controlling and maintaining a constant slew rate at an output of a buffer is provided. The method includes the following steps: (a) receiving, (i) a first input signal and (ii) at least one of a control voltage using the buffer; (b) generating a threshold voltage using a first reference voltage generator; (c) comparing (i) the threshold voltage with an output of the buffer using at least one of a comparator; (d) determining a phase difference using a phase detector; (e) producing a DC voltage using a loop filter; (f) generating a reference voltage; (g) receiving the DC voltage and the reference voltage using an amplifier; (h) amplifying the difference between (a) said DC voltage, and (b) the reference voltage to obtain a control voltage using the amplifier; and (i) feeding the control voltage to the buffer.

Slew rate locked loop

A method and system for protecting low voltage devices driven by a high voltage circuit is disclosed. The method comprises monitoring an output voltage, from a high voltage block, to a low voltage block. The method further comprises comparing the output voltage with a range of voltages allowable for driving the low voltage block. The range of voltages may be pre-defined or dynamically determined. Furthermore, the method comprises operating a first set of switches and a second set of switches. The first set of switches are operated to feed voltage from the high voltage block to input of the low voltage block, and the second set of switches are operated to feed a plurality of reference voltages to the input of the low voltage block.

Protection circuit for low voltage devices driven by a high voltage circuit

A method and system for linearizing a Radio Frequency Power Amplifier (RFPA) is disclosed. The method comprises calibrating signals in the RFPA to linearize the RFPA, using at least one of a first signal, a second signal, a third signal, and a fourth signal. The first signal is generated corresponding to ambient temperature. The second signal is generated corresponding to process corner of transistors in the RFPA. The third signal is generated corresponding to power supply voltage. The fourth signal is generated by feeding back output of the RFPA.

Method and system for linearizing a radio frequency power amplifier

Methods and circuits for maximizing gain of a voltage follower circuit are provided. The method includes using a NMOS voltage replica generation circuit, a PMOS voltage replica generation circuit, a NPN BJT voltage replica generation circuit, a n-channel JFET voltage replica generation circuit, a P-Channel JFET voltage replica generation circuit and a PNP BJT voltage replica generation circuit. The overall gain for the various transistor families is almost equal to unity.

Voltage follower circuit to mitigate gain loss caused by finite output impedance of transistors

A method and system of synthesizing impedance in a radio frequency (RF) amplifier includes receiving a voltage signal at a passive mixer. The passive mixer down-converts the voltage signal into a baseband frequency. The method includes converting the voltage signal into a digital signal. Further, the method includes performing convolution of the digital signal with an impulse response. The impulse response is of a low Q impedance and is programmable. Furthermore the method includes generating a current signal based on output of the convolution. Furthermore the method includes performing up-conversion of the current signal in the passive mixer. The passive mixer performs impedance transformation of the low Q impedance. Moreover, the method includes providing the current signal via the passive mixer to synthesize desired impedance in the RF amplifier, thereby controlling frequency response of the RF amplifier.

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Bengaluru, India

Himamshu Gopalakrishna Khasnis