International Business Machines Corporation

Globalfoundries Inc.

Hillery C Hunter

Kyu-hyoun Kim

Charles Arthur Kilmer

Warren Edward Maule

Michael B Healy

Michele M Franceschini

Luis Alfonso Lastras-Montano

Paul William Coteus

Ashish Jagmohan

Vijayalakshmi Srinivasan

Jeffrey A Stuecheli

Saravanan Sethuraman

Ravi Nair

Alper Buyuktosunoglu

Pradip Bose

Benjiman L Goodman

Jude A Rivers

Moinuddin K Qureshi

Xiaochen Guo

Daniel Mark Dreps

William John Starke

Kevin Charles Gower

Philip George Emma

James Allan Kahle

Philip Heidelberger

John Kenneth DeBrosse

Kenneth Lee Wright

Adam J McPadden

David Michael Daly

Janani Mukundan

Peter Anthony Sandon

George L Chiu

Arnold S Tran

Venkata K Tavva

Kyu-Hyoun Kim

Rona Yaari

John Ulrich Knickerbocker

John Steven Dodson

Hubertus Franke

Karthick Rajamani

Diyanesh B Chinnakkonda Vidyapoornachary

Erik L Hedberg

Hartmut Penner

Gokul Bhargava Kandiraju

Stephen P Glancy

Luis A Lastras

Kaoutar El Maghraoui

Saurabh Chadha

Abhijit Saurabh

Phillip Stanley-Marbell

Vipin Patel

Vipinchandra Patel

Daniel Christopher Worledge

John Edward Barth, Jr

Todd Edward Takken

Nataraj Nagaratnam

Chitra K Subramanian

William Robert Reohr

Dinakaran B Joseph

William Eric Hall

Shawn Anthony Hall

Stephen J Powell

Douglas James Joseph

Glen Arthur Wiedemeier

Joab Daniel Henderson

Ronald Pete Luijten

Marc Raymond Faucher

Ronald Peter Luijten

Steven Powell

Michael S Law

John E Barth

Adam Robert Geiger

Priyank Narvekar

A method, apparatus, system, and computer program product for configuring a computing environment. A configuration profile is identified by a computer system for the computing environment that is to be deployed in which the computing environment meets a security policy to run an application in the computing environment. A determination is made, by the computer system, as to whether the configuration profile for the computing environment meets the security policy for running the application in the computing environment. The configuration profile for the computing environment is deployed, by the computer system, to configure the computing environment for the application in response to the configuration profile meeting the security policy.

Security compliance for a secure landing zone

A flash translation layer method, system, and computer program product, include performing a virtualization of a meta-flash translation layer by: instantiating a range in a NAND chip comprising the number of free blocks using a meta-FTL to create a compatible range of blocks for a type of a feature and a flash characteristic of a translation table if a number of free blocks are available in the NAND chip and instantiating a second range in the NAND chip comprising a second number of free blocks using the meta-FTL to create a second compatible range of blocks for a second type of feature and a second flash characteristic of the translation table, and dynamically programming data on the fly based on an input requirement of a request into the range and the second range.

System, method and computer program product for instantiating blocks of a solid-state disk to include different flash characteristics

A system and method for storing data that includes at least one memory device having a plurality of memory cells for storing data; and a memory control circuit that manages the read current and read pulse width applied to the memory cells, wherein the at least one memory device has a read current circuit configured to utilize adjustments to at least one of the read current or the read pulse width applied to the memory cells. In response to a request to read a group of the memory cells, the memory control circuit in an example, in response to determining that a comparative temperature value exceeds a first threshold, is configured to perform at least one of reducing the read current and/or increasing the read pulse width to be applied to the group of memory devices to be read.

Method and system to improve read reliability in memory devices

A computer-implemented method, according to one embodiment, includes: determining a current temperature associated with an intended storage location in memory for data in a write request, determining a percentage of first logical states included in a binary representation of the data in the received write request, selecting a write management operation in response to determining that the current temperature associated with the intended storage location is outside a predetermined range, and sending one or more instructions to perform the write management operation. Moreover, the write management operation corresponds to the determined percentage of first logical states included in the binary representation. Other systems, methods, and computer program products are described in additional embodiments.

Write management for increasing non-volatile memory reliability

Examples of techniques for an integrated wafer-level processing system are disclosed. In one example implementation according to aspects of the present disclosure, an integrated wafer-level processing system includes a memory wafer and a processing element connected to the memory wafer via a data connection.

Integrated wafer-level processing system

A flash translation layer method, system, and computer program product, include sending a request with a type of feature and a flash characteristic of a translation table for a Solid-State disk, receiving, via a meta-flash translation layer (meta-FTL), the request and checking for a number of free blocks in a NAND chip, and instantiating a range in the NAND chip including the number of free blocks using the meta-FTL to create a compatible range of blocks for the type of feature and the flash characteristic of the translation table if the checking returns a confirmation that the number of free blocks is available.

A computer-implemented method, according to one embodiment, includes: receiving a write request, determining an intended storage location in memory for data in the received write request, determining a current temperature associated with the intended storage location, determining a percentage of first logical states included in a binary representation of the data in the received write request, selecting a write management operation in response to determining that the current temperature associated with the intended storage location is outside a predetermined range, and sending one or more instructions to perform the write management operation. Moreover, the write management operation corresponds to the determined percentage of first logical states included in the binary representation. Other systems, methods, and computer program products are described in additional embodiments.

Examples of techniques for a built-in self-test (BIST) for embedded spin-transfer torque magnetic random access memory (STT-MRAM) are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: initiating, by a processor, a BIST for the STT-MRAM; performing, by the processor, an error-correcting code (ECC) test for a portion of the STT-MRAM; responsive to the ECC test not being passed, determining whether a maximum signal is reached; responsive to the maximum signal not being reached, increasing the signal and performing the ECC test again; and responsive to the maximum signal being reached, determining that the portion of the STT-MRAM is bad.

Built-in self-test for embedded spin-transfer torque magnetic random access memory

Techniques for improving the security of nonvolatile memory such as magnetic random access memory (MRAM) are provided. In one aspect, a method of operating a nonvolatile memory chip is provided. The method includes: overwriting data stored on the nonvolatile memory chip automatically upon the nonvolatile memory chip being powered on. For example, all bits in the nonvolatile memory chip can be written to either i) a predetermined data state (e.g., a logic 1 or a logic 0) or ii) a random data state. A system is also provided that includes: a nonvolatile memory chip; and a writing circuit configured to overwrite data stored on the nonvolatile memory chip automatically upon the nonvolatile memory chip being powered on.

Secure off-chip MRAM

A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.

Implementing selective cache injection

An aspect includes determining a configuration change to at least one memory device of a memory system. A band switch enable command is sent from a memory controller to the at least one memory device indicating the configuration change. One or more internal circuits of the at least one memory device are set into a quiescent mode based on receiving the band enable command. One or more of a voltage and a frequency of the at least one memory device are adjusted to implement the configuration change. A band switch disable command is sent from the memory controller to the at least one memory device based on completing the adjusting. The one or more internal circuits are enabled to operate using the adjustment based on receiving the band switch disable command from the memory controller.

Memory system with switchable operating bands

A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ECC) bits and an extended correction table. The extended correction table stores error information additional to the ECC bits for one or more of the data in the memory array. The system also includes a controller to control the memory device to write and read the data.

Extended error correction coding data storage

Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.

Error monitoring of a memory device containing embedded error correction

Growing community of inventors

Deerfield, IL, United States of America

Hillery C Hunter